Cypress CY7C1298H CY7C1298H

CY7C1298H

Document #: 38-05665 Rev. *B Page 2 of 16

Functional Block DiagramADDRESSREGISTER

ADV

CLK BURST

COUNTER AND

LOGIC

CLR

ADSC

BWB

BWA

CE1

DQB, DQPB

BYTE

WRITE REGISTER

DQA , DQPA

BYTE

WRITE REGISTER

ENABLE

SENSE

AMPS

MEMORY

ARRAY

ADSP

2A[1:0]

MODE

CE2

CE3

BWE

PIPELINED

ENABLE

DQs,

DQP

OUTPUT

REGISTERS

INPUT

REGISTERS

E

OUTPUT

BUFFERS

DQB , DQPB

BYTE

WRITE DRIVER

DQA, DQPA

BYTE

WRITE DRIVER

SLEEP

CONTROL

A

0, A1, A

[+] Feedback

Contents

Main 1-Mbit (64K x 18) Pipelined DCD Sync SRAM CY7C1298H Features Functional Description Selection Guide CY7C1298H Functional Block Diagram A E ADDRESS REGISTER CY7C1298H A Pin Descriptions Functional Overview Burst Sequences Sleep Mode Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) Truth Table CY7C1298H Truth Table for Read/Write ZZ Mode Electrical Characteristics CY7C1298H Maximum Ratings Operating Range Electrical Characteristics CY7C1298H Capacitance Thermal Characteristics AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Read Timing [+] Feedback CY7C1298H Write Timing Read/Write Timing ZZ Mode Timing Ordering Information Package Diagram A Document History Page