Cypress CY7C1298H ZZ Mode Timing

CY7C1298H

Document #: 38-05665 Rev. *B Page 14 of 16

ZZ Mode Timing[20, 21]

Notes:

20.Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.

21.I/Os are in High-Z when exiting ZZ sleep mode.

Switching Waveforms (continued)

tZZ

ISUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q) High-Z

DESELECT or READ Only

[+] Feedback

Contents

Main 1-Mbit (64K x 18) Pipelined DCD Sync SRAM CY7C1298H Features Functional Description Selection Guide CY7C1298H Functional Block Diagram A E ADDRESS REGISTER CY7C1298H A Pin Descriptions Functional Overview Burst Sequences Sleep Mode Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) Truth Table CY7C1298H Truth Table for Read/Write ZZ Mode Electrical Characteristics CY7C1298H Maximum Ratings Operating Range Electrical Characteristics CY7C1298H Capacitance Thermal Characteristics AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Read Timing [+] Feedback CY7C1298H Write Timing Read/Write Timing ZZ Mode Timing Ordering Information Package Diagram A Document History Page