PRELIMINARY CY7C1333H
Document #: 001-00209 Rev. ** Page 3 of 12
Pin Definitions (100-pin TQFP Package)
Name I/O Description
A0, A1, A Input-
Synchronous Address Inputs used to select one of the 64K address locations. Sampled at the rising edge
of the CLK. A[1:0] are fed to the two-bit burst counter.
BW[A:D] Input-
Synchronous Byte Write Inputs, active LOW. Qualified with WE to conduct Writes to the SRAM. Sampled on
the rising edge of CLK.
WE Input-
Synchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a Write sequence.
ADV/LD Input-
Synchronous Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD should be
driven LOW in order to load a new address.
CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
is only recognized if CEN is active LOW.
CE1Input-
Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2, and CE3 to select/deselect the device.
CE2Input-
Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
CE3Input-
Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
OE Input-
Asynchronous Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins.
OE is masked during the data portion of a Write sequence, during the first clock when emerging
from a deselected state, when the device has been deselected.
CEN Input-
Synchronous Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
ZZ Input-
Asynchronous ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin can be connected to VSS or left
floating.
DQsI/O-
Synchronous Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by address during the clock rise of the Read cycle. The direction of the pins is controlled
by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs.
When HIGH, DQs are placed in a three-state condition. The outputs are automatically three-stated
during the data portion of a Write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE.
Mode Input
Strap Pin Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved
burst sequence.
VDD Power Supply Power supply inputs to the core of the device.
VDDQ I/O Power
Supply Power supply for the I/O circuitry.
VSS Ground Ground for the device.
NC –No Connects. Not Internally connected to the die.
4M, 9M,18M,36M, 72M, 144M, 256M, 576M and 1G are address expansion pins and are not
internally connected to the die.
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