Cypress CY7C1333H Capacitance, AC Test Loads and Waveforms , Switching Characteristics

PRELIMINARY CY7C1333H
Document #: 001-00209 Rev. ** Page 8 of 12
Capacitance[11]
Parameter Description Test Conditions 100 TQFP Package Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 3.3V
VDDQ=3.3V
5pF
CCLOCK Clock Input Capacitance 5 pF
CI/O I/O Capacitance 5 pF
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range[12, 13]
Parameter Description
133 MHz 100 MHz
UnitMin. Max. Min. Max.
tPOWER VDD(Typical) to the First Access[14] 1 1 ms
Clock
tCYC Clock Cycle Time 7.5 10 ns
tCH Clock HIGH 2.5 4.0 ns
tCL Clock LOW 2.5 4.0 ns
Output Times
tCDV Data Output Valid after CLK Rise 6.5 8.0 ns
tDOH Data Output Hold after CLK Rise 2.0 2.0 ns
tCLZ Clock to Low-Z[15, 16, 17] 0 0 ns
tCHZ Clock to High-Z15, 16, 17] 3.5 3.5 ns
tOEV OE LOW to Output Valid 3.5 3.5 ns
tOELZ OE LOW to Output Low-Z[15, 16, 17] 0 0 ns
tOEHZ OE HIGH to Output High-Z[15, 16, 17] 3.5 3.5 ns
Set-up Times
tAS Address Set-up before CLK Rise 1.5 2.0 ns
tALS ADV/LD Set-up before CLK Rise 1.5 2.0 ns
tWES WE, BW[A:D] Set-up before CLK Rise 1.5 2.0 ns
tCENS CEN Set-up before CLK Rise 1.5 2.0 ns
tDS Data Input Set-up before CLK Rise 1.5 2.0 ns
tCES Chip Enable Set-Up before CLK Rise 1.5 2.0 ns
Notes:
12.Timing reference level is 1.5V when VDDQ=3.3V
13.Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
14.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation
can be initiated.
15.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
16.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Three-state prior to Low-Z under the same system conditions
17.This parameter is sampled and not 100% tested.
OUTPUT
R = 317Ω
R = 351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50Ω
Z0= 50Ω
V
L
= 1.5V
3.3V ALL INPUT PULSES
VDDQ
GND
90%
10% 90%
10%
≤1 ns ≤1 ns
(c)
3.3V I/O Test Load
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