Cypress CY7C1333H manual Capacitance, AC Test Loads and Waveforms

			PRELIMINARY		CY7C1333H
Capacitance[11]
Parameter		Description		Test Conditions	100 TQFP Package	Unit
CIN	Input Capacitance			TA = 25°C, f = 1 MHz,	5	pF
				VDD = 3.3V
CCLOCK	Clock Input Capacitance				5	pF
				VDDQ=3.3V
CI/O	I/O Capacitance				5	pF

AC Test Loads and Waveforms

3.3V I/O Test Load

OUTPUT

3.3V

R = 317Ω

ALL INPUT PULSES

VDDQ

Z0

= 50Ω

OUTPUT

RL

= 50Ω

10%

90%

5 pF

R = 351Ω

GND

≤ 1 ns

VL = 1.5V

INCLUDING

(c)

(a)

JIG AND

(b)

SCOPE

Switching Characteristics Over the Operating Range [12, 13]

90%

10%

≤ 1 ns

		133 MHz		100 MHz
Parameter	Description	Min.	Max.	Min.	Max.	Unit
tPOWER	VDD(Typical) to the First Access[14]	1		1		ms
Clock

tCYC	Clock Cycle Time	7.5	10
tCH	Clock HIGH	2.5	4.0
tCL	Clock LOW	2.5	4.0
Output Times

ns

ns

ns

tCDV

tDOH

tCLZ

tCHZ

tOEV

tOELZ

tOEHZ

Data Output Valid after CLK Rise			6.5		8.0	ns
Data Output Hold after CLK Rise		2.0		2.0		ns
Clock to Low-Z[15, 16, 17]		0		0		ns
Clock to High-Z15, 16, 17]			3.5		3.5	ns
OE	LOW to Output Valid		3.5		3.5	ns
	LOW to Output Low-Z[15, 16, 17]	0		0		ns
OE
	HIGH to Output High-Z[15, 16, 17]		3.5		3.5	ns
OE

Set-up Times

tAS	Address Set-up before CLK Rise				1.5	2.0
tALS
	ADV/LD			Set-up before CLK Rise	1.5	2.0
tWES				[A:D] Set-up before CLK Rise	1.5	2.0
	WE,		BW
tCENS	CEN	Set-up before CLK Rise			1.5	2.0
tDS	Data Input Set-up before CLK Rise				1.5	2.0
tCES	Chip Enable Set-Up before CLK Rise				1.5	2.0

Notes:

12.Timing reference level is 1.5V when VDDQ=3.3V

13.Test conditions shown in (a) of AC Test Loads, unless otherwise noted.

ns

ns

ns

ns

ns

ns

14.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation can be initiated.

15.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

16.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve Three-state prior to Low-Z under the same system conditions

17.This parameter is sampled and not 100% tested.

Document #: 001-00209 Rev. ** Page 8 of 12

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