PRELIMINARY CY7C1333H
Document #: 001-00209 Rev. ** Page 5 of 12
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Interleaved Burst Sequence
First
Address Second
Address Third
Address Fourth
Address
A1, A0 A1, A0 A1, A0 A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
IDDZZ Sleep mode standby current ZZ > VDD − 0.2V 40 mA
tZZS Device operation to ZZ ZZ > VDD − 0.2V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns
tZZI ZZ Active to sleep current This parameter is sampled 2tCYC ns
tRZZI ZZ inactive to exit sleep current This parameter is sampled 0 ns
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation ADDRESS
Used CE1CE2 CE3ZZ ADV/LD WE BWXOE CEN CLK DQ
Deselect Cycle None H X X L L X X X L L->H Three-State
Deselect Cycle None X X H L L X X X L L->H Three-State
Deselect Cycle None X L X L L X X X L L->H Three-State
Continue Deselect
Cycle None X X X L H X X X L L->H Three-State
READ Cycle
(Begin Burst) External L H L L L H X L L L->H Data Out (Q)
READ Cycle
(Continue Burst) Next X X X L H X X L L L->H Data Out (Q)
NOP/DUMMY READ
(Begin Burst) External L H L L L H X H L L->H Three-State
DUMMY READ
(Continue Burst) Next X X X L H X X H L L->H Three-State
WRITE Cycle
(Begin Burst) External L H L L L L L X L L->H Data In (D)
WRITE Cycle
(Continue Burst) Next X X X L H X L X L L->H Data In (D)
NOP/WRITE ABORT
(Begin Burst) No ne L H L L L L H X L L->H Three-State
WRITE ABORT
(Continue Burst) Next X X X L H X H X L L->H Three-State
IGNORE CLOCK
EDGE (Stall) Current X X X L X X X X H L->H -
Sleep MODE None X X X H X X X X X X Three-State
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write
Selects are asserted, see Truth Table for details.
3. Write is defined by BW[A:D], and WE. See Truth Table for Read/Write.
4. When a Write cycle is detected, all I/Os are three-stated, even during Byte Writes.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle DQs = Three-state when OE is inactive
or when the device is deselected, and DQs = data when OE is active.
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