Cypress CY7C1410AV18 manual Logic Block Diagram CY7C1412AV18, Logic Block Diagram CY7C1414AV18

CY7C1410AV18, CY7C1425AV18

CY7C1412AV18, CY7C1414AV18

Logic Block Diagram (CY7C1412AV18)

18

D[17:0]

20

A(19:0)

K

K

DOFF

VREF

WPS

BWS[1:0]

Address Register

CLK

Gen.

Control

Logic

	Write	Write
	Reg	Reg
Write Add. Decode	1M x 18 Array	1M x 18 Array
	Read Data Reg.
		36
		18
		18

Read Add. Decode

Reg.

Reg.

Address Register

Control

Logic

Reg.

20 A(19:0)

RPS

C

C

CQ

18 CQ

18 18 Q[17:0]

Logic Block Diagram (CY7C1414AV18)

36

D[35:0]

19Address

A(18:0) Register

K

K CLK

Gen.

DOFF

VREF		Control
WPS
		Logic
BWS
	[3:0]

Write Add. Decode

Write		Write
Reg		Reg
512K x		512K x	Decode
36 Array		36 Array	Read Add.
Read Data Reg.
	72	36
				Reg.
		36
				Reg.

Address Register

Control

Logic

Reg.

19 A(18:0)

RPS

C

C

CQ

36 CQ

36 36 Q[35:0]

Document #: 38-05615 Rev. *E Page 3 of 29

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