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Cypress CY7C1410AV18, CY7C1412AV18, CY7C1414AV18, CY7C1425AV18 Package Diagram

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CY7C1410AV18, CY7C1425AV18

CY7C1412AV18, CY7C1414AV18

Document #: 38-05615 Rev. *E Page 27 of 29

Package Diagram

Figure 6. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85195

PIN1CORNER

17.00±0.10

15.00±0.10

7.00

1.00

Ø0.50 (165X)

Ø0.25MC A B

Ø0.05MC

0.15(4X)

0.35±0.06

1.40MAX.

SEATINGPLANE

0.53±0.05

0.25C

0.15C

PIN1CORNER

TOPVIEW BOTTOMVIEW

2345678910

10.00

14.00

1110986754321

1.00

5.00

0.36

+0.14

-0.06

SOLDERPADTYPE : NON SOLDER MASK DEFINED (NSMD)

NOTES:

PACKAGEWEIGHT: 0.65g

JEDECREFERENCE: MO-216 / DESIGN 4.6C

PACKAGECODE: BB0AD

51-85195-*A

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Contents

Main 36-Mbit QDR-II SRAM 2-Word Burst Architecture CY7C1410AV18, CY7C1425AV18 CY7C1412AV18, CY7C1414AV18 Features Configurations Functional Description CY7C1410AV18, CY7C1425AV18 CY7C1412AV18, CY7C1414AV18 Document #: 38-05615 Rev. *E Page 2 of 29 Logic Block Diagram (CY7C1410AV18) Logic Block Diagram (CY7C1425AV18) Document #: 38-05615 Rev. *E Page 3 of 29 Logic Block Diagram (CY7C1412AV18) Logic Block Diagram (CY7C1414AV18) CY7C1410AV18, CY7C1425AV18 CY7C1412AV18, CY7C1414AV18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1410AV18, CY7C1425AV18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout Pin Definitions CY7C1410AV18, CY7C1425AV18 CY7C1412AV18, CY7C1414AV18 Pin Definitions CY7C1410AV18, CY7C1425AV18 CY7C1412AV18, CY7C1414AV18 Functional Overview Read Operations Write Operations Byte Write Operations Application Example SRAM #2 SRAM #1 BUS MASTER (CPU or ASIC) CY7C1410AV18, CY7C1425AV18 Truth Table Write Cycle Descriptions Page CY7C1412AV18, CY7C1414AV18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Page CY7C1410AV18, CY7C1425AV18 CY7C1412AV18, CY7C1414AV18 TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1410AV18, CY7C1425AV18 CY7C1412AV18, CY7C1414AV18 Boundary Scan Order Power Up Sequence in QDR-II SRAM VV Power Up Sequence DLL Constraints / Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics Electrical Characteristics DC Electrical Characteristics Capacitance Thermal Resistance Switching Characteristics Document #: 38-05615 Rev. *E Page 24 of 29 Switching Waveforms Figure 5. Read/Write/Deselect Sequence 1234 5810 67 READ READ WRITE WRITEWRITE NOPREAD WRITE NOP 9 CY7C1410AV18, CY7C1425AV18 Ordering Information Document #: 38-05615 Rev. *E Page 27 of 29 Package Diagram [+] Feedback Figure 6. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85195 51-85195-*A Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Document History Page