Cypress CY7C1420AV18 Logic Block Diagram CY7C1416AV18, Logic Block Diagram CY7C1427AV18, Doff

CY7C1416AV18, CY7C1427AV18

CY7C1418AV18, CY7C1420AV18

Logic Block Diagram (CY7C1416AV18)

21

A(20:0)

LD

K

K

DOFF

VREF

R/W

NWS[1:0]

Address Register

CLK

Gen.

Control

Logic

	Write	Write
Decode	Reg	Reg	Decode
	2M x	2M x			8
WriteAdd.	8Array	8Array	ReadAdd.	Logic
				Output	R/W
	Read Data Reg.			Control	C
					C

16
8	Reg.		Reg.	8		CQ
						CQ
8					8
	Reg.	8				DQ[7:0]

Logic Block Diagram (CY7C1427AV18)

21

A(20:0)

LD

K

K

DOFF

VREF

R/W

BWS[0]

Address Register

CLK

Gen.

Control

Logic

	Write	Write
Decode	Reg	Reg	Decode
	2M x	2M x			9
WriteAdd.	9Array	9Array	ReadAdd.	Logic
				Output	R/W
	Read Data Reg.			Control	C
					C

18
9	Reg.		Reg.	9		CQ
						CQ
9					9
	Reg.	9				DQ[8:0]

Document Number: 38-05616 Rev. *F Page 2 of 31

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