CY7C1416AV18, CY7C1427AV18

 

 

 

 

 

 

 

 

 

 

CY7C1418AV18, CY7C1420AV18

 

 

 

 

 

 

 

 

 

 

Pin Definitions (continued)

 

 

 

 

 

 

 

 

 

 

Pin Name

IO

 

 

 

 

 

Pin Description

 

CQ

Output Clock

CQ Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock

 

 

 

 

 

for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing

 

 

 

 

 

for the echo clocks is shown in the Switching Characteristics on page 23.

 

CQ

 

 

Output Clock

CQ

Referenced with Respect to

C

. This is a free-running clock and is synchronized to the input clock

 

 

 

 

 

for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing

 

 

 

 

 

for the echo clocks is shown in the Switching Characteristics on page 23.

 

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

 

 

 

 

 

impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected

 

 

 

 

 

between ZQ and ground. Alternatively, connect this pin directly to VDDQ, which enables the minimum

 

 

 

 

 

impedance mode. This pin cannot be connected directly to GND or left unconnected.

 

DOFF

 

Input

DLL Turn Off Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing

 

 

 

 

 

in the DLL turned off operation differs from those listed in this data sheet.

 

TDO

Output

TDO for JTAG.

 

 

 

 

 

TCK

Input

TCK Pin for JTAG.

 

TDI

Input

TDI Pin for JTAG.

 

 

 

 

 

TMS

Input

TMS Pin for JTAG.

 

 

 

 

 

NC

N/A

Not Connected to the Die. Tie to any voltage level.

 

NC/72M

N/A

Not Connected to the Die. Tie to any voltage level.

 

 

 

 

 

NC/144M

N/A

Not Connected to the Die. Tie to any voltage level.

 

 

 

 

 

NC/288M

N/A

Not Connected to the Die. Tie to any voltage level.

 

VREF

Input-

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC

 

 

 

 

Reference

measurement points.

 

 

 

 

 

VDD

Power Supply

Power Supply Inputs to the Core of the Device.

 

VSS

Ground

Ground for the Device.

 

VDDQ

Power Supply

Power Supply Inputs for the Outputs of the Device.

Document Number: 38-05616 Rev. *F

Page 7 of 31

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Page 7
Image 7
Cypress CY7C1427AV18 manual Referenced with Respect to, TDO for Jtag, TCK Pin for Jtag, TDI Pin for Jtag, TMS Pin for Jtag