CY7C1416AV18, CY7C1427AV18
CY7C1418AV18, CY7C1420AV18
Document Number: 38-05616 Rev. *F Page 24 of 31
Output Times
tCO tCHQV C/C Clock Rise (or K/K in single
clock mode) to Data Valid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
tDOH tCHQX Data Output Hold after Output C/C
Clock Rise (Active to Active) –0.4
5– –0.4
5––0.4
5– –0.4
5––0.5
0–ns
tCCQO tCHCQV C/C Clock Rise to Echo Clock Valid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
tCQOH tCHCQX Echo Clock Hold after C/C Clock
Rise –0.4
5– –0.4
5––0.4
5– –0.4
5––0.5
0–ns
tCQD tCQHQV Echo Clock High to Data Valid – 0.27 – 0.27 – 0.30 – 0.35 – 0.40 ns
tCQDOH tCQHQX Echo Clock High to Data Invalid –0.2
7– –0.2
7––0.3
0– –0.3
5––0.4
0–ns
tCHZ tCHQZ Clock (C/C) Rise to High-Z
(Active to High-Z) [24, 25] – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns
tCLZ tCHQX1 Clock (C/C) Rise to Low-Z [24, 25] –0.4
5– –0.4
5––0.4
5– –0.4
5––0.5
0–ns
DLL Timing
tKC Var tKC Var Clock Phase Jitter – 0.20 – 0.20 – 0.20 – 0.20 – 0.20 ns
tKC lock tKC lock DLL Lock Time (K, C) 1024 – 1024 – 1024 – 1024 – 1024 – Cycle
s
tKC Reset tKC Reset K Static to DLL Reset 30–30–30–30–30– ns
Switching Characteristics (continued)
Over the Operating Range [20, 21]
Cypress
Parame-
ter
Consor-
tium Pa-
rameter Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit
Min Max Min Max Min Max Min Max Min Max
Notes
24.tCHZ, tCLZ are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms on page 22. Transition is measured ±100 mV from steady-state voltage.
25.At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
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