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Cypress CY7C1416AV18, CY7C1418AV18, CY7C1420AV18, CY7C1427AV18 Switching Waveforms

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CY7C1416AV18, CY7C1427AV18

CY7C1418AV18, CY7C1420AV18

Document Number: 38-05616 Rev. *F Page 25 of 31

Switching Waveforms

Figure 5. Read/Write/Deselect Sequence [26, 27, 28]

READ READREAD NOP NOP WRITEWRITE

NOP

12345678910

Q40

tKHCH

tCO

ttHC

ttHA

tSD

tHD

tKHCH

tSD

tHD

DON’T CARE UNDEFINED

tCLZ tDOH tCHZ

tKH tKHKH

tKL tCYC

D20 D21 D30 D31

Q00 Q11Q01 Q10

A1 A2 A3 A4

Q41

tCCQO

tCQOH

tCCQO

tCQOH

tKL tCYC

R/W

CQ#

tKH tKHKH

tCQD

tCQDOH

Notes

26.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

27.Outputs are disabled (High-Z) one clock cycle after a NOP.

28.In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.

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Contents

Main 36-Mbit DDR-II SRAM 2-Word Burst Architecture CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18 Features Configurations Functional Description CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18 Logic Block Diagram (CY7C1416AV18) Logic Block Diagram (CY7C1427AV18) 2M x 8 Array 2M x 8 Array 2M x 9 Array 2M x 9 Array Logic Block Diagram (CY7C1418AV18) Logic Block Diagram (CY7C1420AV18) 1M x 18 Array 1M x 18 Array 512K x 36 Array 512K x 36 Array CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1416AV18, CY7C1427AV18 Pin Definitions CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18 Pin Definitions CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18 Functional Overview Read Operations for DDR-II Write Operations Byte Write Operations Application Example BUS MASTER (CPU or ASIC) Truth Table Burst Address Table Page IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Test D ata- In (T DI) Page CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18 TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical Characteristics CY7C1416AV18, CY7C1427AV18 TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18 Boundary Scan Order Power Up Sequence in DDR-II SRAM VV Power Up Sequence DLL Constraints / CY7C1418AV18, CY7C1420AV18 Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics Electrical Characteristics DC Electrical Characteristics Capacitance Thermal Resistance Page Switching Characteristics Switching Waveforms Figure 5. Read/Write/Deselect Sequence READ READREAD NOP NOP WRITEWRITE NOP 12345678910 Ordering Information CY7C1416AV18, CY7C1427AV18 Ordering Information Package Diagram Figure 6. 165-ball FBGA (15 x 17 x 1.4 mm), 51-85195 [+] Feedback 51-85195-*A Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Document History Page