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Cypress CY7C1510JV18, CY7C1512JV18, CY7C1514JV18, CY7C1525JV18 CY7C1510JV18, CY7C1525JV18

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CY7C1510JV18, CY7C1525JV18

CY7C1512JV18, CY7C1514JV18

Document #: 001-14435 Rev. *C Page 25 of 26

Package Diagram

Figure 4. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195

PIN1CORNER

17.00±0.10

15.00±0.10

7.00

1.00

Ø0.50 (165X)

Ø0.25MC A B

Ø0.05MC

0.15(4X)

0.35±0.06

1.40MAX.

SEATINGPLANE

0.53±0.05

0.25C

0.15C

PIN1CORNER

TOPVIEW BOTTOMVIEW

2345678910

10.00

14.00

1110986754321

1.00

5.00

0.36

+0.14

-0.06

SOLDERPADTYPE : NON SOLDER MASK DEFINED (NSMD)

NOTES:

PACKAGEWEIGHT: 0.65g

JEDECREFERENCE: MO-216 / DESIGN 4.6C

PACKAGECODE: BB0AD

51-85195-*A

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Contents

Main 72-Mbit QDR-II SRAM 2-Word Burst Architecture CY7C1510JV18, CY7C1525JV18 CY7C1512JV18, CY7C1514JV18 Features Configurations Functional Description CY7C1510JV18, CY7C1525JV18 CY7C1512JV18, CY7C1514JV18 Document #: 001-14435 Rev. *C Page 2 of 26 Logic Block Diagram (CY7C1510JV18) Logic Block Diagram (CY7C1525JV18) Document #: 001-14435 Rev. *C Page 3 of 26 Logic Block Diagram (CY7C1512JV18) Logic Block Diagram (CY7C1514JV18) CY7C1512JV18, CY7C1514JV18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1510JV18, CY7C1525JV18 CY7C1512JV18, CY7C1514JV18 Pin Configuration 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout Pin Definitions CY7C1510JV18, CY7C1525JV18 CY7C1512JV18, CY7C1514JV18 V V Pin Definitions CY7C1510JV18, CY7C1525JV18 CY7C1512JV18, CY7C1514JV18 Functional Overview Read Operations Write Operations Byte Write Operations Application Example SRAM #2 SRAM #1 BUS MASTER (CPU or ASIC) CY7C1510JV18, CY7C1525JV18 Truth Table Write Cycle Descriptions Page CY7C1512JV18, CY7C1514JV18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Page CY7C1512JV18, CY7C1514JV18 TAP Controller State Diagram CY7C1510JV18, CY7C1525JV18 CY7C1512JV18, CY7C1514JV18 TAP Controller Block Diagram TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1510JV18, CY7C1525JV18 CY7C1512JV18, CY7C1514JV18 Boundary Scan Order Power Up Sequence in QDR-II SRAM VV Power Up Sequence DLL Constraints Power Up Waveforms Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Document #: 001-14435 Rev. *C Page 23 of 26 Switching Waveforms Figure 3. Read/Write/Deselect Sequence 1234 5810 67 READ READ WRITE WRITEWRITE NOPREAD WRITE NOP 9 Ordering Information CY7C1510JV18, CY7C1525JV18 Document #: 001-14435 Rev. *C Page 25 of 26 [+] Feedback [+] Feedback Package Diagram Figure 4. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 Document History Page