Cypress CY7C1510JV18 manual REV ECN no Issue ORIG. Description of Change Date, Vkn/Aesa

CY7C1510JV18, CY7C1525JV18

CY7C1512JV18, CY7C1514JV18

Document History Page

Document Title: CY7C1510JV18/CY7C1525JV18/CY7C1512JV18/CY7C1514JV18, 72-Mbit QDR™-II SRAM 2-Word

Burst Architecture

Document Number: 001-14435

REV.	ECN NO.	ISSUE	ORIG. OF	DESCRIPTION OF CHANGE
		DATE	CHANGE
**	1060980	See ECN	VKN	New Data Sheet
*A	1397384	See ECN	VKN	Added 267MHz speed bin
*B	1462588	See ECN	VKN/AESA	Converted from preliminary to final
				Removed 200MHz speed bin
				Updated IDD/ISB specs
				Changed DLL minimum operating frequency from 80MHz to 120MHz
				Changed tCYC max spec to 8.4ns for all speed bins
*C	2189567	See ECN	VKN/AESA	Minor Change-Moved to the external web

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Document #: 001-14435 Rev. *C Revised March 10, 2008 Page 26 of 26

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.

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