Cypress CY7C1512JV18, CY7C1514JV18, CY7C1510JV18 manual Application Example, Echo Clocks, Sram #1

CY7C1510JV18, CY7C1525JV18

CY7C1512JV18, CY7C1514JV18

Echo Clocks DLL

Echo clocks are provided on the QDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock of the QDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in Switching Characteristics on page 22.

These chips use a DLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the DLL to lock to the desired frequency. The DLL automatically locks 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in QDR-I mode (with one cycle latency and a longer access time). For information refer to the application note DLL Considerations in QDRII/DDRII.

Application Example
Figure 1 shows two QDR-II used in an application.
			Figure 1. Application Example
			SRAM #1		ZQ	R = 250ohms		SRAM #2		ZQ	R = 250ohms
	Vt		R W B		CQ/CQ#		R W B			CQ/CQ#
		D	P P W		Q	D	P	P W		Q
			S S S				S	S S
	R
		A	# # #	C C# K K#		A	# # #		C C# K K#
	DATA IN
	DATA OUT						Vt
	Address						Vt
BUS	RPS#						R
	WPS#
MASTER
	BWS#
(CPU
	CLKIN/CLKIN#
or	Source K
ASIC)
	Source K#
	Delayed K
	Delayed K#
	R	R = 50ohms	Vt = Vddq/2

Document #: 001-14435 Rev. *C Page 9 of 26

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