Document #: 001-06981 Rev. *D Revised June 14, 2008 Page 30 of 30
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CY7C1522AV18, CY7C1529AV18
CY7C1523AV18, CY7C1524AV18
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Document History Page
Document Title: CY7C1522AV18/CY7C1529AV18/CY7C1523AV18/CY7C1524AV18, 72-Mbit DDR-II SIO SRAM 2-Word
Burst Architecture
Document Number: 001-06981
REV. ECN NO. SUBMISSION
DATE ORIG. OF
CHANGE DESCRIPTION OF CHANGE
** 433241 See ECN NXR New Data Sheet
*A 462002 See ECN NXR Changed tTCYC from 100 ns to 50 ns, changed tTH and tTL from 40 ns to 20 ns,
changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV
from 20 ns to 10 ns in TAP AC Switching Characteristics table
Modified Power-Up waveform
*B 503690 See ECN VKN Minor change: Moved data sheet to web
*C 1523363 See ECN VKN/AESA Converted from preliminary to final
Updated Logic Block diagram
Updated IDD/ISB specs
Changed DLL minimum operating frequency from 80MHz to 120MHz
Changed tCYC max spec to 8.4ns for all speed bins
Modified footnotes 20 and 28
*D 2509289 See ECN VKN/AESA Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to
“–55°C to +125°C” in the “Maximum Ratings “ on page 20, Updated Power-up
sequence waveform and it’s description, Added footnote #19 related to IDD,
Changed ΘJA spec from 16.2 to 16.3, Changed ΘJC spec from 2.3 to 2.1,
Changed JTAG ID [31:29] from 001 to 000.
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