PRELIMINARY CY7C2561KV18, CY7C2576KV18
CY7C2563KV18, CY7C2565KV18
Document Number: 001-15887 Rev. *E Page 24 of 29
Switching Characteristics
Over the Operating Range [24, 25]
Cypress
Parameter
Consortium
Parameter Description 550 MHz 500 MHz 450 MHz 400 MHz Unit
Min Max Min Max Min Max Min Max
tPOWER VDD(Typical) to the First Access [26] 1111ms
tCYC tKHKH K Clock Cycle Time 1.81 8.4 2.0 8.4 2.2 8.4 2.5 8.4 ns
tKH tKHKL Input Clock (K/K) HIGH 0.4 – 0.4 – 0.4 – 0.4 – ns
tKL tKLKH Input Clock (K/K) LOW 0.4 – 0.4 – 0.4 – 0.4 – ns
tKHKHtKHKHK Clock Rise to K Clock Rise
(rising edge to rising edge)
0.77 – 0.85 – 0.94 – 1.06 – ns
Setup Times
tSA tAVKH Address Setup to K Clock Rise 0.23 – 0.25 – 0.275 – 0.4 – ns
tSC tIVKH Control Setup to K Clock Rise (RPS, WPS)0.23 – 0.25 – 0.275 – 0.4 – ns
tSCDDR tIVKH Double Data Rate Control Setup to Clock (K/K)
Rise (BWS0, BWS1, BWS2, BWS3)
0.18 – 0.20 – 0.22 – 0.28 – ns
tSD tDVKH D[X:0] Setup to Clock (K/K) Rise 0.18 – 0.20 – 0.22 – 0.28 – ns
Hold Times
tHA tKHAX Address Hold after K Clock Rise 0.23 – 0.25 – 0.275 – 0.4 – ns
tHC tKHIX Control Hold after K Clock Rise (RPS, WPS) 0.23 – 0.25 – 0.275 – 0.4 – ns
tHCDDR tKHIX Double Data Rate Control Hold after Clock (K/K)
Rise (BWS0, BWS1, BWS2, BWS3)
0.18 – 0.20 – 0.28 – 0.28 – n s
tHD tKHDX D[X:0] Hold after Clock (K/K) Rise 0.18 – 0.20 – 0.28 – 0.28 – n s
Output Times
tCO tCHQV K/K Clock Rise to Data Valid – 0.29 – 0.33 – 0.37 – 0.45 ns
tDOH tCHQX Data Output Hold after Output K/K Clock Rise
(Active to Active)
–0.29 – –0.33 – –0.37 – –0.45 – ns
tCCQO tCHCQV K/K Clock Rise to Echo Clock Valid – 0.29 – 0.33 – 0.37 – 0.45 ns
tCQOH tCHCQX Echo Clock Hold after K/K Clock Rise –0.29 – –0.33 – –0.37 – –0.45 – ns
tCQD tCQHQV Echo Clock High to Data Valid 0.15 0.15 0.15 0.20 ns
tCQDOH tCQHQX Echo Clock High to Data Invalid –0.15 – –0.15 – –0.15 – –0.20 – ns
tCQH tCQHCQL Output Clock (CQ/CQ) HIGH [27] 0.655 – 0.75 – 0.85 – 1.0 – ns
tCQHCQHtCQHCQHCQ Clock Rise to CQ Clock Rise
(rising edge to rising edge) [27] 0.655 – 0.75 – 0.85 – 1.0 – ns
tCHZ tCHQZ Clock (K/K) Rise to High-Z
(Active to High-Z) [28, 29]
– 0.29 – 0.33 – 0.37 – 0.45 ns
tCLZ tCHQX1 Clock (K/K) Rise to Low-Z [28, 29] –0.29 – –0.33 – –0.37 – –0.45 – ns
tQVLD tCQHQVLD Echo Clock High to QVLD Valid [30] –0.15 0.15 –0.15 0.15 –0.15 0.15 –0.20 0.20 ns
PLL Timing
tKC Var tKC Var Clock Phase Jitter – 0.15 – 0.15 – 0.15 – 0.20 ns
tKC lock tKC lock PLL Lock Time (K) 20–20–20–20– μs
tKC Reset tKC Reset K Static to PLL Reset [31] 30 30 30 30 ns
Notes
25.When a part with a maximum frequency above 400 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
26.This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a read or write operation can be
initiated.
27.These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production.
28.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 100 mV from steady-state voltage.
29.At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
30.tQVLD spec is applicable for both rising and falling edges of QVLD signal.
31.Hold to >VIH or <VIL.
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