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| PRELIMINARY | CY7C2561KV18, CY7C2576KV18 | ||||
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| CY7C2563KV18, CY7C2565KV18 | |||||
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TAP AC Switching Characteristics |
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Over the Operating Range [17, 18] |
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| Description |
| Min | Max | Unit | |
tTCYC | TCK Clock Cycle Time |
| 50 |
| ns | |||
tTF | TCK Clock Frequency |
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| 20 | MHz | |||
tTH | TCK Clock HIGH |
| 20 |
| ns | |||
tTL | TCK Clock LOW |
| 20 |
| ns | |||
Setup Times |
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tTMSS | TMS Setup to TCK Clock Rise |
| 5 |
| ns | |||
tTDIS | TDI Setup to TCK Clock Rise |
| 5 |
| ns | |||
tCS | Capture Setup to TCK Rise |
| 5 |
| ns | |||
Hold Times |
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tTMSH | TMS Hold after TCK Clock Rise |
| 5 |
| ns | |||
tTDIH | TDI Hold after Clock Rise |
| 5 |
| ns | |||
tCH | Capture Hold after Clock Rise |
| 5 |
| ns | |||
Output Times |
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tTDOV | TCK Clock LOW to TDO Valid |
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| 10 | ns | |||
tTDOX | TCK Clock LOW to TDO Invalid |
| 0 |
| ns |
TAP Timing and Test Conditions
Figure 4 shows the TAP timing and test conditions. [18]
Figure 4. TAP Timing and Test Conditions
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| 0.9V | |||
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| 50Ω |
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TDO |
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Z0 | = 50Ω |
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| CL = 20 pF | |
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ALL INPUT PULSES
1.8V
0.9V
0V
(a)GND
Test Clock
TCK
Test Mode Select
TMS
Test Data In
TDI
Test Data Out
TDO
tTH
tTMSS
tTDIS
tTL
tTCYC
tTMSH
tTDIH
tTDOV |
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| TDOX |
Notes
17.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
18.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: | Page 17 of 29 |
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