Cypress CY7C2561KV18, CY7C2563KV18, CY7C2565KV18, CY7C2576KV18 PRELIMINARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18

PRELIMINARY CY7C2561KV18, CY7C2576KV18
CY7C2563KV18, CY7C2565KV18
Document Number: 001-15887 Rev. *E Page 2 of 29
Logic Block Diagram (CY7C2561KV18)
Logic Block Diagram (CY7C2576KV18)
2M x 8 Array
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
21
32
8
NWS[1:0]
VREF
Write Add. Decode
Write
Reg
16
A(20:0)
21
2M x 8 Array 2M x 8 Array 2M x 8 Array
8
CQ
CQ
DOFF
Q[7:0]
8
QVLD
8
8
8
Write
Reg
Write
Reg
Write
Reg
Q[8:0]
9
2M x 9 Array
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
21
36
9
BWS[0]
VREF
Write Add. Decode
Write
Reg
18
A(20:0)
21
2M x 9 Array 2M x 9 Array 2M x 9 Array
9
CQ
CQ
DOFF
QVLD
9
9
9
Write
Reg
Write
Reg
Write
Reg
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