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Cypress CY7C2561KV18, CY7C2563KV18, CY7C2565KV18, CY7C2576KV18 - page 27

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PRELIMINARY CY7C2561KV18, CY7C2576KV18

CY7C2563KV18, CY7C2565KV18

Document Number: 001-15887 Rev. *E Page 27 of 29

450 CY7C2561KV18-450BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C2576KV18-450BZC

CY7C2563KV18-450BZC

CY7C2565KV18-450BZC

CY7C2561KV18-450BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C2576KV18-450BZXC

CY7C2563KV18-450BZXC

CY7C2565KV18-450BZXC

CY7C2561KV18-450BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C2576KV18-450BZI

CY7C2563KV18-450BZI

CY7C2565KV18-450BZI

CY7C2561KV18-450BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C2576KV18-450BZXI

CY7C2563KV18-450BZXI

CY7C2565KV18-450BZXI

400 CY7C2561KV18-400BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C2576KV18-400BZC

CY7C2563KV18-400BZC

CY7C2565KV18-400BZC

CY7C2561KV18-400BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C2576KV18-400BZXC

CY7C2563KV18-400BZXC

CY7C2565KV18-400BZXC

CY7C2561KV18-400BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C2576KV18-400BZI

CY7C2563KV18-400BZI

CY7C2565KV18-400BZI

CY7C2561KV18-400BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C2576KV18-400BZXI

CY7C2563KV18-400BZXI

CY7C2565KV18-400BZXI

Table 11. Ordering Information (continued)

Speed

(MHz) Ordering Code

Package

Diagram Package Type

Operating

Range

[+] Feedback

Contents

Main 72-Mbit QDR-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT PRELIMINARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Features Configurations PRELIMINARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Document Number: 001-15887 Rev. *E Page 2 of 29 Logic Block Diagram (CY7C2561KV18) Logic Block Diagram (CY7C2576KV18) CY7C2563KV18, CY7C2565KV18 Logic Block Diagram (CY7C2563KV18) Logic Block Diagram (CY7C2565KV18) Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout PRELIMINARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Pin Configuration 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout Page PRELIMINARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 NC NC PRELIMINARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Functional Overview Read Operations Write Operations Byte Write Operations Depth Expansion Programmable Impedance Echo Clocks Valid Data Indicator (QVLD) On-Die Termination (ODT) Application Example SRAM #1 SRAM #2 BUS MASTER (CPU orASIC) Page Page IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access PortTest Clock Test Mode Select (TMS) Test D ata- In ( TDI) Page Page TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions PRELIMINARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Page Power Up Sequence in QDR-II+ SRAM VV Power Up Sequence PLL Constraints / Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Electrical Characteristics Capacitance Thermal Resistance Electrical Characteristics DC Electrical Characteristics AC Test Loads and Waveforms ZQ ZQ [+] Feedback RQ = 250 (b) RQ = 250 Switching Characteristics PRELIMINARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 Switching Waveforms QVLD NOPREAD RPS Ordering Information Page Package Diagram Figure 7. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 [+] Feedback SOLDERPAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40MAX. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Document History Page