CY7C68000A
Document #: 38-08052 Rev. *G Page 11 of 15
HS/FS Interface Timing - 30 MHz
Figure 4. 30 MHz Timing Interface Timing Constraints
Figure 5. Tri-state Mode Timing Constraints
Table 5. Tri-state Mode Timing Constraints Parameters
Table 4. 30 MHz Timing Interface Timing Constraints Parameters
Parameter Description Min Typ Max Unit Notes
TCSU_MIN Minimum setup time for TXValid 16 ns
TCH_MIN Minimum hold time for TXValid 1 ns
TDSU_MIN Minimum setup time for Data (Transmit direction) 16 ns
TDH_MIN Minimum hold time for Data (Transmit direction) 1 ns
TCCO Clock to Control Out time for TXReady, RXValid,
RXActive and RXError
120ns
TCDO Clock to Data out time (Receive direction) 1 20 ns
TVSU_MIN Minimum setup time for ValidH (transmit Direction) 16 ns
TVH_MIN Minimum hold time for ValidH (Transmit direction) 1 ns
TCVO Clock to ValidH out time (Receive direction) 1 20 ns
Parameter Description Min Typ Max Unit Notes
Ttssu Minimum setup time for Tri-state 0 ns
Ttspd Propagation Delay for Tri-State mode 50 ns
TCSU_MIN
TCH_MIN
TDSU_MIN
TDH_MIN
TCVO
TCCO
DataIn
DataOut
Control_Out
Control_In
CLK
TCDO
TVSU_MIN
TVH_MIN

Ttssu Ttspd Ttspd

Suspend

Tri-state

Output / IO XXXX Hi-Z

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