Cypress CY7C68000A specifications Pin Configurations

CY7C68000A

Pin Configurations

The following pages illustrate the individual pin diagrams that are available in the 56-pin QFN and 56-pin VFBGA packages. The packages offered use either an 8-bit (60 MHz) or 16-bit (30 MHz) bus interface.

Figure 1. CY7C68000A 56-pin QFN Pin Assignment

TXReady

Suspend

Reset

AVCC

XTALOUT

XTALIN

AGND

AVCC

DPLUS

DMINUS

AGND

XcvrSelect

TermSelect

OpMode0

	ValidH	CC		TXValid	GND	Unibidi	DataBus168	CLK	D0	D1	Reserved	D2	CC	D3	D4
			V										V
	56		55	54	53	52	51	50	49	48	47	46	45	44	43
1																42
2																41
3																40
4																39
5																38
6							CY7C68000A									37
7							56-pin QFN									36
8																35
9																34
10																33
11																32
12																31
13																30
14																29
	15		16	17	18	19	20	21	22	23	24	25	26	27	28

GND

D5 Reserved D6

D7

D8

D9 Reserved D10 D11

VCC

D12

GND

D13

GND OpMode1	V	RXError RXActive RXValid GND LineState1 LineState0	D14 D15 Reserved Tri state	V
	CC			CC

Document #: 38-08052 Rev. *G Page 4 of 15

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