DATA BRIEF | CY7C68003 |
MoBL-USB™ TX2UL USB 2.0
ULPI Transceiver
Features
The Cypress
The TX2UL is specifically designed for mobile handset applications by offering tiny package options and low power consumption.
■USB 2.0 Full Speed and High Speed Compliant Transceiver
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■Fully Compliant ULPI Link Interface
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■UTMI+ Level 0 Support
■Integrated Oscillator
■Integrated PLL (13, 19.2, 24, or 26 MHz Reference)
■Integrated USB Pull Up and Termination Resistors
■3.0V to 5.775V VBATT Input
■Chip Select Pin
■Single Ended Device RESET Input
■UART Pass Through Mode
■ESD Compliance:
❐
❐
❐
■Support for Industrial Temperature Range
■Low Power Consumption for Mobile Applications:
❐5 uA Nominal Sleep Mode
❐30 mA Nominal Active HS Transfer
■Small Package for Mobile Applications:
❐2.14 x 1.76 mm
❐4 x 4 mm
Applications
■Mobile Phones
■PDAs
■Portable Media Players (PMPs)
■DTV Applications
■Portable GPS Units
TX2UL Block Diagram
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| TX2UL |
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| CLOCK |
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| ULPI Block |
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| DATA[7:0] |
| IO | Operational | Tx/Rx |
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| Control/ | mode |
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| DP |
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| DIR |
| Data | tracking | Core |
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| USB |
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| Logic | interrupt |
| UTMI+ |
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| STP |
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| FS/HS |
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| Registers |
| Level0 |
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| NXT |
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| PHY | DM |
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| Block |
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| ULPI Wrapper |
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| RXD |
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| TXD |
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| RESET_N |
| Global Control Block |
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| Reset / Clock / Power / |
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| CS_N |
| 3.3V Regulator |
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| Misc. Control |
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(3.0 – | VBATT |
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| Block |
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5.775V) | VCC | POR |
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| 1.8V |
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| (1.8V) |
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| XI |
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| PLL |
| Bandgap |
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13/19.2/ | XOSC |
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XO |
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24/26 MHz |
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Cypress Semiconductor Corporation | • | 198 Champion Court | • | San Jose, CA | • |
Revised April 1, 2009