Cypress CY7C68003 manual VID and PID, Ulpi Low Power Mode, Sleep Mode

CY7C68003

The operation and configuration modes are described in Operation Modes on page 4 and Configuration Mode on page 14 respectively. The ULPI Low power mode and Sleep mode are described in the following sections:

ULPI Low Power Mode

In this mode, the link optionally places the TX2UL in low power mode when the USB is suspended. TX2UL powers down all the circuitry except for the interface pins and full speed receiver. To enter low power mode, the link must set SuspendM in the Function Control register to 0b. The TX2UL clock is stopped for a minimum of five cycles after TX2UL accepts the register write. To exit the low power mode, the link signals TX2UL to exit the mode by asynchronously asserting a signal, STP. The TX2UL wakes up its internal circuitry and when it meets the ULPI timing requirements it deasserts DIR. The SuspendM register is set to 1b.

Sleep Mode

Sleep mode is entered by asserting RESET_N during the Normal Operation Mode. When RESET_N is driven low for tSTATE (see Table 21 on page 19 for tSTATE requirement) while CS_N is low, TX2UL enters into Sleep Mode. VCC must remain supplied (ON) during the sleep mode. This mode powers down all internal circuitry except the RESET_N pin and the chip_config register. The ULPI interface bus is tri-stated.

During the Sleep Mode ensure that:

■The ULPI interface IOs is either floating or driven high by the link

■DP and DM are either floating or pull to 0V

■Deassert RESET_N to exit the Sleep Mode.

VID and PID

The VID and PID are hard coded into Product ID and Vendor ID registers (read only) as shown in Table 6.

Table 6. Immediate Register Values for VID and PID

Field Name	Size (bit)		Address (6 bits)			Value
		Rd	Wr	Set	Clr
Vendor ID (VID) Low	8	00h	-	-	-	B4h
Vendor ID (VID) High	8	01h	-	-	-	04h
Product ID (PID) Low	8	02h	-	-	-	03h
Product ID (PID) High	8	03h	-	-	-	68h

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Revised April 1, 2009 Page 5 of 5

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