CY7C68023/CY7C68024
3.2Pin Descriptions (continued)
Pin | Name | Type | Default State at | Description |
16 | Reserved | N/A | N/A | Must be tied HIGH (no |
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17 | VCC | PWR | PWR | 3.3V supply |
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18 | DDO | I/O | Z | Data 0 |
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19 | DD1 | I/O | Z | Data 1 |
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20 | DD2 | I/O | Z | Data 2 |
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21 | DD3 | I/O | Z | Data 3 |
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22 | DD4 | I/O | Z | Data 4 |
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23 | DD5 | I/O | Z | Data 5 |
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24 | DD6 | I/O | Z | Data 6 |
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25 | DD7 | I/O | Z | Data 7 |
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26 | GND | GND | GND | Ground |
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27 | VCC | PWR | PWR | 3.3V supply |
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28 | GND | GND | GND | Ground |
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29 | WE# | O | H | Write enable |
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30 | RE0# | O | H | Read Enable 0 |
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31 | RE1# | O | H | Read Enable 1 |
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32 | VCC | PWR | PWR | 3.3V supply |
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33 | CLE | O | Z | Command latch enable |
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34 | ALE | O | Z | Address latch enable |
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35 | LED1# | O | Z | Data activity LED sink |
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36 | LED2# | O | Z | Chip active LED sink |
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37 | WP_NF# | O | Z | |
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38 | WP_SW# | I | Z | |
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39 | N/C | N/A | N/A | No connect |
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40 | N/C | N/A | N/A | No connect |
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41 | GND | GND | GND | Ground |
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42 | RESET# | I | Z | NX2LP chip reset |
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43 | VCC | PWR | PWR | 3.3V supply |
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44 | Reserved | N/A | N/A | Must be tied HIGH |
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45 | CE0# | O | Z | Chip enable 0 |
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46 | CE1# | O | Z | Chip enable 1 |
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47 | CE2# | O | Z | Chip enable 2 |
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48 | CE3# | O | Z | Chip enable 3 |
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49 | CE4# | O | Z | Chip enable 4 |
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50 | CE5# | O | Z | Chip enable 5 |
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51 | CE6# | O | Z | Chip enable 6 |
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52 | CE7# | O | Z | Chip enable 7 |
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53 | GND | GND | GND | Ground |
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54 | N/C | N/A | N/A | No connect |
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55 | VCC | PWR | PWR | 3.3V supply |
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56 | GND | GND | GND | Ground |
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Document #: | Page 3 of 9 |
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