Cypress STK12C68 manual AC Switching Characteristics, Switching Waveforms, SRAM Read Cycle

							STK12C68
AC Switching Characteristics
SRAM Read Cycle
Parameter		Description	25 ns		35 ns		45 ns		Unit
Cypress	Alt		Min	Max	Min	Max	Min	Max
Parameter
tACE	tELQV	Chip Enable Access Time		25		35		45	ns
tRC [7]	tAVAV, tELEH	Read Cycle Time	25		35		45		ns
tAA [8]	tAVQV	Address Access Time		25		35		45	ns
tDOE	tGLQV	Output Enable to Data Valid		10		15		20	ns
tOHA [8]	tAXQX	Output Hold After Address Change	5		5		5		ns
tLZCE [9]	tELQX	Chip Enable to Output Active	5		5		5		ns
tHZCE [9]	tEHQZ	Chip Disable to Output Inactive		10		10		12	ns
tLZOE [9]	tGLQX	Output Enable to Output Active	0		0		0		ns
tHZOE [9]	tGHQZ	Output Disable to Output Inactive		10		10		12	ns
tPU [6]	tELICCH	Chip Enable to Power Active	0		0		0		ns
tPD [6]	tEHICCL	Chip Disable to Power Standby		25		35		45	ns

Switching Waveforms

Figure 7. SRAM Read Cycle 1: Address Controlled [7, 8]

$''5(66

W5&

W$$

W2+$

'4'$7$287

'$7$9$/,'

Figure 8. SRAM Read Cycle 2: CE and OE Controlled [7]

$''5(66

&(

2(

'4'$7$287

,&&

W5&

W$&(

W/=&(

W'2(

W/=2(

W38 $&7,9(

67$1'%<

W3'

W+=&(

W+=2(

'$7$9$/,'

Notes

7.WE and HSB must be High during SRAM Read cycles.

8.Device is continuously selected with CE and OE both Low.

9.Measured ±200 mV from steady state output voltage.

Document Number: 001-51027 Rev. ** Page 9 of 20

[+] Feedback