Cypress STK12C68 Pin Configurations, Pin Definitions, 28-Pin SOIC/DIP and LLC, Pin Name, IO Type

STK12C68

Pin Configurations

Figure 1. 28-Pin SOIC/DIP and LLC

Pin Definitions

Pin Name

Alt

IO Type

Description

A0–A12

Input

Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.

DQ0-DQ7

Input or Output

Bidirectional Data IO Lines. Used as input or output lines depending on operation.

Input

Write Enable Input, Active LOW. When the chip is enabled and

is LOW, data on the IO

WE

WE

W

pins is written to the specific address location.

Input

Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.

CE

E

Input

Output Enable, Active LOW. The active LOW

input enables the data output buffers during

OE

OE

G

read cycles. Deasserting OE HIGH causes the IO pins to tri-state.

VSS

Ground

Ground for the Device. The device is connected to ground of the system.

VCC

Power Supply

Power Supply Inputs to the Device.

Input or Output

Hardware Store Busy

(HSB)

. When LOW, this output indicates a Hardware Store is in progress.

HSB

When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal

pull up resistor keeps this pin high if not connected (connection optional).

VCAP

Power Supply

AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM

to nonvolatile elements.

Document Number: 001-51027 Rev. ** Page 2 of 20

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