Cypress STK14D88 manual SRAM WRITE Cycle #1 and #2

STK14D88

SRAM WRITE Cycle #1 and #2

NO.		Symbols		Parameter	STK14D88-25		STK14D88-35		STK14D88-45		Unit
	#1	#2	Alt.		Min	Max	Min	Max	Min	Max
12	tAVAV	tAVAV	tWC	Write Cycle Time	25		35		45		ns
13	tWLWH	tWLEH	tWP	Write Pulse Width	20		25		30		ns
14	tELWH	tELEH	tCW	Chip Enable to End of Write	20		25		30		ns
15	tDVWH	tDVEH	tDW	Data Set-up to End of Write	10		12		15		ns
16	tWHDX	tEHDX	tDH	Data Hold after End of Write	0		0		0		ns
17	tAVWH	tAVEH	tAW	Address Set-up to End of Write	20		25		30		ns
18	tAVWL	tAVEL	tAS	Address Set-up to Start of Write	0		0		0		ns
19	tWHAX	tEHAX	tWR	Address Hold after End of Write	0		0		0		ns
20	tWLQZ[6, 8]		tWZ	Write Enable to Output Disable		10		13		15	ns
21	tWHQX		tOW	Output Active after End of Write	3		3		3		ns

Figure 6. SRAM WRITE Cycle 1: W Controlled [8, 9]

ADDRESS

E

W

DATA IN

DATA OUT

			12
			tAVAV
			14	19
				tWHAX
			tELWH
		17
18		tAVWH
tAVWL		13
		tWLWH
			15	13
			tDVWH	tWHDX
		20	DATA VALID
		tWLQZ		21
			HIGH IMPEDANCE	tWHQX
	PREVIOUS DATA

Figure 7. SRAM WRITE Cycle 2: E Controlled [8, 9]

		12
		tAVAV
ADDRESS
18		14	19
tAVEL		tELEH	tEHAX
E
	17
	tAVEH	13
W		tWLEH
		15	16
		tDVEH	tEHDX
DATA IN			DATA VALID
DATA OUT		HIGH IMPEDANCE

Notes

8.If W is low when E goes low, the outputs remain in the high-impedance state.

9.E or W must be ≥ VIH during address transitions.

Document Number: 001-52037 Rev. ** Page 6 of 17

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