DFI PM12-EC, PM12-EL CPU & PCI Bus Control, CPU to PCI Write Buffer, PCI Master 0 WS Write

Award BIOS Setup Utility

3.1.3.3 CPU & PCI Bus Control

Move the cursor to this field and press <Enter>. The following screen will appear

Phoenix - AwardBIOS CMOS Setup Utility

CPU & PCI Bus Control

CPU to PCI Write Buffer		Enabled		Item Help
PCI Master 0 WS Write		Enabled		Menu Level
PCI Delay Transaction		Disabled
↑↓→← Move Enter:Select	+/-/PU/PD:Value F10:Save		ESC:Exit F1:General Help
F5:Previous Values		F6:Fail-Safe Defaults	F7:Optimized Defaults

The settings on the screen are for reference only. Your version may not be identical to this one.

CPU to PCI Write Buffer

Enabled Writes from the CPU to the PCI bus are buffered to offset the speed difference between the CPU and PCI bus.

Disabled Writes are not buffered therefore the CPU must wait until the write cycle is complete before starting another write cycle.

PCI Master 0 WS Write

When enabled, writes to the PCI bus are executed with zero wait state.

PCI Delay Transaction

When enabled, this function frees up the PCI bus for other PCI masters during the PCI-to-ISA transactions. This allows PCI and ISA buses to be used more efficiently and prevents degradation of performance on the PCI bus when ISA accesses are made.

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