EM78612Universal Serial Bus Microcontroller
10 •
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•Product Specification(V1.0)03.2 2.2006
(This specification is subject to changewithout further notice)
R0 (Indirection Add ressing Reg ister)
R1 (Time Clock / C ounter Regi ster)
R2 (Program Cou nter) & Stac k
R3 (Status Registe r)
R4 (RAM Select Reg ister)
R5 (Data line I/O R egister)
R6 (Port 6 I/O Reg ister)
R7 (Port 7 I/O Reg ister)
R8 (Port6 wakeu p pin select ion Register )
R9 (Port7 wakeu p pin select ion Register )
RC (USB Application Status Reg ister)
RD (USB Application FIFO addre ss register )
RE (USB Application FIFO data register)
RF (Interrupt Stat us Register)
00
01
02
03
04
05
06
07
08
General Purpose Register
09
0C
0D
0F
0E
IOC5 (Port 5 I/O Control Reg ister)
IOC6 (Port 6 I/O Control Reg ister)
IOC7 (Port 7 I/O Control Reg ister)
IOC8 (Sink Cure nt Control Re gister)
IOCA (Operation m ode Contro l Register)
IOCB (Port 6 pu ll low Cont rol Register )
IOCC (Port 6 pu ll high Cont rol Register )
IOCD (Port 7 pu ll high Cont rol Register )
IOCE (Special F unction Con trol Register )
IOCF (Interrupt M ask Registe r)
EP0's FIFO
EP1's FIFO
Data Byte Pointer o f EP0
00
01
10
1F
20
General Purpos e
Registers
(Bank0)
General Purpos e
Registers
(Bank1)
3F
Data Byte Pointer o f EP111
10
Fig 7-1 The Organization of EM78612 Data RAM
7.2.1.1 Operation Registers in Bank 0
The following introduces each of the Operation Registers under the Special Purpose
Registers. The Operati on Registers are arranged according to the order of registers’
address. Note that some registers are read only, while others are both readable and
writable.
R0 (Indirect Address Register) Default Value: (0B_0000_0000)
R0 is not a physicall y implemented register. Its major function is to be an indirect
address pointer. Any instruction using R0 as a pointer actually accesses the data
pointed by the RAM Select Register (R4).
R1 (Time / Clock Counter) Default Value: (0B_0000_0000)
This register TCC, is an 8-bit timer or counter. It is readable and writable as any other
register. The Timer module will increment every instruction cycle . The user can work
around this by writing an adjusted value. The Timer interrupt is generated when the R1
register overflows from FFh to 00h. This overflow sets bit TCIF(RF[0]). The int errupt
can be masked by clearing bit TCIE (IO CF[0]).After Power-on reset and WatchDog
reset, the initial value of this register is 0x00.