LX-105O+ Service Manual Operating Principles
2.3.2.5
Printhead
Drive Circuit
Gate array
E05A30
is used as an 8-bit + l-bit data latch. The CPU determines the pulse width for
the head-wire drive pulses from gate array
E05A30
by monitoring the
printhead
drive power (+24
V line).
The
E05A30
gate array includes circuitry to interface the CPU and the
printhead.
The data is output
to the
printhead
in the following sequence:
Print data is expanded in the image buffer as dot patterns. The CPU outputs the dot patterns to the
E05A30.
The data for pins 1 through 8 of the
printhead
is latched by HDl trough
HD8
of the
E05A30.
The data for pin 9 of the
printhead
is latched by
HD9
of the
E05A30.
After data latching, the pnnthead drive pulse width signal FIRE is output from the CPU’s event
counter. When the signal is LOW, the gate array will be open, so that the data from
HD1
through
HD9
will be output.
The drive pulse width is adjusted using CPU port PC6.
CPU
/
U
PD78 10HG
(2C)
--N
DATA
-1/
FIRE
EO%30
(3 B)

--N

--l/

Printhead
Drive
Circuit
Print herd
L
Figure 2-17. Printhead Drive Circuit Block Diagram
Rev.
A2-13