Operating Principles
LX-105O+
Service Manual
2.3.2.6 Host Interface
The host
interface circuit is
shown in following figure. STROBE
pulses
from the host computer pass
through the low-pass filter, consisting of R72 and C12, and flow into the STROBE terminal.
These pulses latch the parallel data and set the BUSY signal HIGH, so that subsequent data transfer
is inhibited.
At this time, the CPU, by reading address
OCO02H,
can detect whether the data from the computer
are latched in the gate array.
When the CPU determines that data have been latched, it proceeds to read the data. After the data
have been read, the gate array automatically resets its busy signal.
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Figure 2-18. Host Interface
2-14
Rev.
A