FOCUS Enhancements FS453, FS454, FS455, FS456 5.1 FS453 GCC Pin Mapping

FS453/4 AND FS455/6 DATA SHEET: HARDWARE REFERENCE

5.1 FS453 ⇔ GCC Pin Mapping

Table 3 below maps the FS453 pins to the host GCC controller chip.

FBGA

Pin # PQFP

Pin # FS453

Pin Name AMD

Alchemy

Pin Name

Freescale

Dragonball

Pin Name

Intel DVO

Pin Name Intel

XScale

Pin

Name

VIA

Pin

Name

D13 56 CLKOUT GPIO EXTAL16M TVCLKIN TVCLK

E13 54 CLKIN_P LCD_PCLK LSCLK CLKOUT0 L_PCLK TVCLKR

G12 51 CLKIN_N CLKOUT1

N9 35 HSYNC LCD_LCLK LP_HSYNC

TVHSYNC L_LCLK TVHS

M10 36 VSYNC LCD_FCLK FLM_VSYNC

TVVSYNC L_FCLK TVVS

M11 38 BLANK LCD_BIAS BLANK BLANK

D2 5 P0 LCD_D16 LT VDATA0 TVDAT0

E1 6 P1 LCD_D17 LTVDATA1 TVDAT1

E2 7 P2 LCD_D18 LTVDATA2 TVDAT2

F1 8 P3 LCD_D19 LD12 LTVDATA3 LDD_11 TVDAT3

F2 9 P4 LCD_D20 LD13 LTVDATA4 LDD_12 TVDAT4

G1 10 P5 LCD_D21 LD14 LTVDATA5 LDD_13 TVDAT5

G2 11 P6 LCD_D22 LD15 LTVDATA6 LDD_14 TVDAT6

H1 12 P7 LCD_D23 LD16 LTVDATA7 LDD_15 TVDAT7

H2 13 P8 LCD_D8 LTVDATA8 TVDAT8

J1 14 P9 LCD_D9 LTVDATA9 TVDAT9

J2 15 P10 LCD_D10 LD6 LTVDATA10 LDD_5 TVDAT10

K1 16 P11 LCD_D11 LD7 LTVDAT A11 LDD_6 TVDAT11

K2 17 P12/ V656_0(a) LCD_D12 LD8 LDD_7

L1 18 P13/ V656_1

LCD_D13 LD9 LDD_8

N3 23 P14/ V656_2

LCD_D14 LD10 LDD_9

M4 24 P15/ V656_3

LCD_D15 LD11 LDD_10

N4 25 P16/ V656_4

LCD_D0

M5 26 P17/ V656_5

LCD_D1

N5 27 P18/ V656_6

LCD_D2

M6 28 P19/ V656_7

LCD_D3 LD0 LDD_0

N6 29 P20 LCD_D4 LD1 L DD_1

M8 32 P21/V656_H

LCD_D5 LD2 LDD_2

N8 33 P22/V656_V

LCD_D6 LD3 LDD_3

M9 34 P23/V656_F

LCD_D7 LD4 LDD_4

K12 45 SCLK GPIO SCL LTVCL SCL SPCLK1

K13 44 SDATA GPIO SDA LTVDA SDA SPD1

Table 3: FS453 to GCC Pin Mapping

(a)Used for ITU-R BT.656 Video output

JANUARY, 2005, VERSION 3.0 16 COPYRIGHT ©2003-4 FOCUS ENHANCEMENTS, INC.

FOCUS Enhancements Semiconductor

Contents

Main FS453/4 and FS455/6 PC-to-TV Video Scan Converter Data Sheet Guides ; The FS453/4 and FS455/6 Hardware Reference is for The FS453/4 and FS455/6 Software/Firmware Reference is for programmers. Table of Contents, Figures & Tables Document Overview 1. Introduction 1.1 General Description 1.2 How does it work? 1.2.1 SDTV Output 1.2.2 HDTV Output 2. Architectural Overview 2.1 Inputs 2.1.1 Input to Output Conversion Matrix 2.2 Color Space Converter 2.3 Patented 2D Scaler 2.4 Patented 2D Flicker Filter 2.5 FIFO 2.6 Post (Horizontal Up) Scaler 2.7 Encoder and Inverse Color Space 2.8 Bi and Tri-Level Sync Insertion (HDTV) 2.12 Serial Control Interface 2.13 Sync Timing Generator 2.14 Input Synchronization 3. Technical Highlights 3.1 Scaling 3.1.1 Video Scaler Challenges 3.1.2 FS453 Solution 3.2 Flicker Reduction 3.2.1 Flicker Filter Challenges 3.2.2 FS453 Solution 3.3 Video Encoding 3.3.1 Encoding Challenges 3.3.2 FS453 Solution 4. Scaling and Positioning Notes 4.1 Vertical Scaling Figure 5: VTOTAL and VACTIVE ratios must match 4.2 Horizontal Scaling 4.3 Vertical and Horizontal Position 5. Pin Assignments Pin Name Pin Name Pin Name Pin Name FS455/6 88 FBGA Bottom View Figure 8 FBGA Pin Diagram 5.1 FS453 GCC Pin Mapping 5.2 Pin Descriptions Page Page Page 6. Control Register Function Map 6.1 Register Reference Table Page Page 7. Specifications 7.1 Absolute Maximum and Recommended Ratings 7.2 Electrical Characteristics Page 7.3 Switching Characteristics 8. Mechanical Dimensions 8.1 80-Lead PQFP Package Page 9. Component Placement 9.1 Power/Ground 9.1.1 Power 9.1.2 Ground 9.2 DIGITAL SIGNALS 9.2.1 Digital Signal Routing 9.2.2 Video Inputs 9.3 ANALOG SIGNALS 9.3.1 Video Output Filters Page 9.4 CLOCK/OSCILLATOR 9.4.1 Reference Crystal Oscillator 9.4.2 FS453 Pixel Clock 9.4.3 Pixel Clock Mode GCC FS453 GCC 9.5 EMI Case Study 9.6 Solder Re-flow Profiles -flow Profile IR Re- IR Re IR Re -flow Profile IR Re- flow Profile 10. Revision History 11. Order Information Critical Applications Policy FOCUS Enhancements, Inc.