FOCUS Enhancements FS453, FS454, FS455, FS456 7.3 Switching Characteristics

FS453/4 AND FS455/6 DATA SHEET: HARDWARE REFERENCE

7.3 Switching Characteristics

Parameter Conditions Min Typ(b) Max Unit

Clocks

fCKIN TV Encoder Reference Clock Frequency 27.0 MHz

fXTOL TV Reference Clock Frequency Tolerance 30 50(c) ppm

tPWHT TV Reference Clock Pulse Width, HIGH 15.0 ns

tPWLT TV Reference Clock Pulse Width, LOW 15.0 ns

fCLKIN Pixel Clock Frequency 40/60 duty cycle 18.0 150.0 MHz

fCORE Scaler Core Frequency(d) 75.0 MHz

fGCKO GCC Clock Output Frequency(a,e,f) GTL, 2.5V and

3.3V scalable 0.78125 150.0 MHz

fGCKO GCC Clock Output Frequency(e,f) 1.8V scalable 0.78125 120.0 MHz

fGCKO GCC Clock Output Frequency(e,f) 1.5V scalable 0.78125 85.0 MHz

tJIT-GCK GCC Clock Output Jitter (peak-to-peak) over a cycle -250 250 ps

DCGCK Duty Cycle 150 MHz 40 60 %

fPLLIN PLL Input Clock Frequency 100 1000 kHz

M PLL Numerator (integer value) 250 3000 N/A

fPLLOUT PLL Output Clock Frequency 100 300 MHz

Reset Assert fCKIN cycles on RESET_L to reset 16 Clocks

Digital Pixel Input Port

tPDH Pixel Clock 0 to Data/Control Hold Time VREF = 0.75V,

1.5V signaling. 0 ns

tPDH Pixel Clock 1 to Data/Control Hold Time VREF = 0.75V,

1.5V signaling. 0 ns

tPSU Pixel Clock 0 to Data/Control Setup Time VREF = 0.75V,

1.5V signaling. 1.2 ns

tPSU Pixel Clock 1 to Data/Control Setup Time VREF = 0.75V,

1.5V signaling. 1.2 ns

Serial Interface

tDAL SCL Pulse Width, LOW 1.3 µs

tDAH SCL Pulse Width, HIGH 0.6 µs

tSTAH SDA Start Hold Time 0.6 µs

tSTASU SCL to SDA Setup Time (Stop) 0.6 µs

tSTOSU SCL to SDA Setup Time (Start) 0.6 µs

tBUFF SDA Stop Hold Time Setup 1.3 µs

tDSU SDA to SCL Data Setup Time 100 ns

tDHO SDA to SCL Data Hold Time 0 ns

Table 8: Switching Characteristics

Notes:

(a) GTL outputs are open drain and are specified with 25 ohm terminations from 1.1 to 1.5 volts and a 15 pF load.

(b) Values shown in Typ column are typical for VDD33 = +3.3V, VDD18 = +1.8V, and TA = 25°C

(d) Scaler Core Frequency = VCO Frequency/PLL_IP

(e) GCC Output Frequency = VCO Frequency/PLL_EP

(f) Scalable (1.5 to 3.3V) LVTTL outputs are specified with a 15 pF load.

FOCUS Enhancements Semiconductor