System Support

4.3.2 Direct Memory Access

Direct Memory Access (DMA) is a method by which a device accesses system memory without involving the microprocessor. Although the DMA method has been traditionally used to transfer blocks of data to or from an ISA I/O device, PCI devices may also use DMA operation as well. The DMA method reduces the amount of CPU interactions with memory, freeing the CPU for other processing tasks.

✎This section describes DMA in general. For detailed information regarding DMA operation, refer to the data manual for the Intel 82801 I/O Controller Hub.

The 82801 ICH6 component includes the equivalent of two 8237 DMA controllers cascaded together to provide eight DMA channels, each (excepting channel 4) configurable to a specific device. Table 4-9 lists the default configuration of the DMA channels.

Table 4-9.

Default DMA Channel Assignments

DMA Channel

Device ID

Controller 1 (byte transfers)

 

0

Spare

1

Audio subsystem

2

Diskette drive

3

Parallel port

 

 

Controller 2 (word transfers)

 

4

Cascade for controller 1

5

Spare

6

Spare

7

Spare

 

 

All channels in DMA controller 1 operate at a higher priority than those in controller 2. Note that channel 4 is not available for use other than its cascading function for controller 1. The DMA controller 2 can transfer words only on an even address boundary. The DMA controller and page register define a 24-bit address that allows data transfers within the address space of the CPU.

In addition to device configuration, each channel can be configured (through PCI Configuration Registers) for one of two modes of operation:

■LPC DMA

■PC/PCI DMA

The LPC DMA mode uses the LPC bus to communicate DMA channel control and is implemented for devices using DMA through the LPC47B397 I/O controller such as the diskette drive controller.

The PC/PCI DMA mode uses the REQ#/GNT# signals to communicate DMA channel control and is used by PCI expansion devices.

The DMA logic is accessed through two types of I/O mapped registers; page registers and controller registers.

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Technical Reference Guide