5

Optimizing a Program

The Optimizer is a program that is an in tegrated part of an MPE/iX compiler. It is a vailable to use with HP C/iX, HP COBOL II/XL, HP F ORTRAN 77/iX, and HP P ascal/iX. When you compile a program, y ou can select an optimizer option that will use the MPE/iX Optimizer to impro ve the code.

This chapter provides an overview of: Techniques a programmer can use to program for best optimization. How Optimizer aids in producing impro ved code.

For detailed information on ho w each compiler optimizes and actions necessary when an optimized program fails, refer to the follo wing manuals in the Language Series:

HP C/iX Reference Manual Supplement (31506-90001).

HP COBOL II/XL Pr ogrammer's Guide (31500-90002).

HP FORTRAN 77/iX Programmer's Guide Supplement (31501-90002). HP Pascal/iX Programmer's Guide (31502-90002).

Note

Symbolic debugging is not a vailable when the optimizer option is selected.

The MPE/iX Optimizer can help a program tak e full advantage of the 900 Series HP Precision Architecture (HP-PA) in the following w ays:

The small instruction set and pipeline arc hitecture allows concurren t execution of multiple instructions. Th us, improved program execution speed can be ac hieved by using careful instruction sc heduling.

Many registers are a vailable in the CPU for fast memory referencing. The Optimizer ma y promote frequently used variables to reside in registers instead of in memory . On the 900 Series, you can optimize at a lev el lower than that whic h is expedient with most commercial optimizers: at compile time, at the mac hine instruction lev el, after instruction selection.

The Optimizer ma y move loop-invariant instructions out of program loops, eliminate redundant calculations, and eliminate unnecessary memory references.

E￿cient instruction sc heduling avoids hardware interlocks and eliminates branc h delay slots, fully utilizing fast instruction cycle time of the 900 Series. Hardw are interlock occurs when two pipelined instructions both require the same resource or when one instruction requires

a result of a previous instruction that has not completed. With a graph of program ￿o w to reveal instruction dependencies, instruction sc heduling can attempt to a void hardware interlocks.

Optimizing a Program 5-1