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OVERVIEW

This chapter introduces the 900 Series HP 3000 and the MPE/iX operating system, describing how they ￿t into the HP 3000 family of computers and MPE operating systems, in general.

It describes hardw are and software naming conventions and pro vides a brief overview of migration to the 900 Series from MPE V/E-based systems. It describes MPE/iX dual operating modes, features, and major subsystems.

It provides an overview of MPE/iX accoun ting structure, session and batc h modes, how to execute MPE/iX commands, and the considerations necessary to con vert ￿les to MPE/iX.

Introduction to the HP 3000

The HP 3000 is a general-purpose m ultiprogramming mac hine, designed for the in teractive, transaction processing en vironment of business and industry . The HP 3000 family of computers includes sev eral models of the mac hine, each with a di￿erent series number.

900 Series HP 3000

The newest high performance mem bers of the 900 Series HP 3000 family are based on HP Precision Architecture (HP-PA), a highly ￿exible computer design that can meet curren t user requirements and requiremen ts arising during future gro wth.

HP Precision Architecture (HP-PA)

HP Precision Architecture (HP-PA) is based on Reduced Instruction Set Computer (RISC) concepts with added extensions for a complete system. This increases computer performance by reducing and simplifying the computer instruction set. HP-P A eliminates system o verhead associated with con ventional computer microcode b y directly implemen ting computer instructions in hardw are. The uniformity of HP-P A instructions enhances pipelining, providing higher performance b y overlapping execution of m ultiple instructions. Man y technologies can implemen t HP-PA; highly integrated VLSI designs can be ac hieved by eliminating the c hip space required for microcode.

High performance from HP-P A architecture results from the memory hierarc hy design and the use of optimizing compilers. Processor w aiting time for memory accesses is minimized due to the following arc hitectural characteristics:

Frequently used instructions and data are stored in a large n umber of CPU registers.

High-speed bu￿ering of code and data occurs.

Optimizing compilers generate e￿cien t object code, allocate registers, and sc hedule instruction sequences to main tain e￿cient pipeline operation.

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