Figure 2-19. Status Register C (Hex 00C)
Bit Function
7 Interrupt request flag
6 Periodic interrupt flag
5 Alarm interrupt flag
4 Update-ended interrupt flag
3–0 Reserved
Note: Interrupts are enabled by bits 6, 5, and 4 in status register B.
Bit 7 If set to 1, this bit indicates that an interrupt has
occurred; bits 6, 5, and 4 indicate the type of interrupt.
Bit 6 If set to 1, this bit indicates that a periodic interrupt has
occurred.
Bit 5 If set to 1, this bit indicates that an alarm interrupt has
occurred.
Bit 4 If set to 1, this bit indicates that an update-ended
interrupt has occurred.
Bits 3–0 These bits are reserved.
Status Register D (Hex 00D)Figure 2-20. Status Register D (Hex 00D)
Bit Function
7 Valid RAM
6–0 Reserved
Bit 7 This read-only bit monitors the internal battery. If set to
1, this bit indicates that the real-time clock has power. If
set to 0, it indicates that the real-time clock has lost
power and the data in CMOS is no longer valid.
Bits 6–0 These bits are reserved.
System Board 2-23