Appendix C. IRQ and DMA channel assignments
Appendix C. IRQ and DMA channel assignments
The following figures list the interrupt request (IRQ) and direct memory access (DMA) assignments.
Figure | 38. IRQ channel assignments | |||||||
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IRQ |
| System | resource |
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NMI |
| Critical | system | error | ||||
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SMI |
| System management interrupt — power management | ||||||
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0 |
| Reserved | (interval | timer) | ||||
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1 |
| Reserved | (keyboard) | |||||
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2 |
| Reserved, | cascade | interrupt from slave PIC | ||||
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3 |
| COM2 | 3 |
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4 |
| COM1 | 3 |
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5 |
| LPT2/audio | (if | present) | ||||
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6 |
| Diskette |
| controller |
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7 |
| LPT1 | 3 |
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8 |
| clock |
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9 |
| Video |
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10 |
| Available |
| to | user |
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11 |
| Available |
| to | user |
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12 |
| Mouse | port |
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13 |
| Reserved | (math | coprocessor) | ||||
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14 |
| Primary | IDE | (if present) | ||||
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15 |
| Secondary | IDE | (if | present) | |||
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Figure | 39. DMA channel assignments |
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DMA channel |
| Data width | System resource | ||
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0 |
| 8 | bits | Open |
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1 |
| 8 | bits | Open |
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2 |
| 8 | bits | Diskette | drive |
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3 |
| 8 | bits | Parallel port (for ECP or EPP) | |
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4 |
| – |
| Reserved | (cascade channel) |
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5 |
| 16 | bits | Open |
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6 |
| 16 | bits | Open |
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7 |
| 16 | bits | Open |
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3 Default, can be changed to another IRQ.
40 | Copyright IBM Corp. September 1999 |
