CPU-Continued
Pin | Port | Description | |
number | name | ||
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| Outputs control signal for the power | |
41 | PWON | switching circuit (MAIN unit; Q24, | |
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| Q23). | |
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42 | NWC | Outputs IF bandwidth control signal. | |
Low : While IF bandwidth is narrow. | |||
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| Outputs control signal for the AF mute | |
43 | AFON | circuit (MAIN unit; Q35, Q36, D29). | |
High : While AF amplifier (MAIN unit; | |||
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| IC8) is activated. | |
OPT3– | I/O ports for the optional board control | ||
OPT1 | signals. | ||
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47 | BUSY | Outputs BUSY detection signal for the | |
optional board via MAIN unit, J1. | |||
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48 | SI | Input port for the clock signal from the | |
optional board via MAIN unit, J1. | |||
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49 | CLI | Input port for the cloning signal. | |
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50 | CLO | Output port for the cloning signal. | |
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51 | POSW | Input for the POWER switch. | |
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| Input port for the remote power control | |
52 | IGSW | signal from external connector (MAIN | |
unit; J6). | |||
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53 | NOIS | Input port for the “NOIS” signal which | |
ºis used noise squelch operation from | |||
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| the FM IF IC (MAIN unit; IC1). | |
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| Input port for the interruption signal | |
54 | CIRQ | from the optional board via MAIN unit, | |
J1. | |||
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55 | CCS | Outputs the chip select signal for the | |
optional board via MAIN unit, J1. | |||
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56 | PTT | Input port for the PTT switch from | |
microphone. | |||
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| Input port for the PTT switch from the | |
57 | EPTT | external connector (MAIN unit; J6). | |
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| Low : External PTT switch is ON. | |
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| Input port for the microphone hanger | |
58 | HANG | detection signal. | |
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| Low ; Microphone on hook. | |
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| Input port for the AF volume control | |
59 | AFVI | (FRONT unit; R14). | |
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| High : [VOL] is maximum clockwise. | |
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60 | CDEC | Input port for CTCSS/DTCS decoding | |
signals. | |||
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61 | SDEC | Input port for the single tone decoding | |
signals. | |||
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62 | OPV1V2 | Input port for the optional board detec- | |
tion signal. | |||
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63 | RSSI | Input port for the detection signal of the | |
received signal strength. | |||
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64 | LVIN | Input port for the PLL lock voltage. | |
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