Intel 21143 Design Considerations, Designing the Ethernet Corner on Motherboards, Design Guide

Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller

6.0Design Considerations

This section provides information to aid the user in designing Ethernet and Fast Ethernet capabilities onto a motherboard. In addition, it also includes design considerations for FCC compliance.

6.1Designing the Ethernet Corner on Motherboards

This subsection provides a list of routing suggestions and a list of component placement suggestions.

The following list contains routing recommendations:

•Minimize the length of high-frequency signals.

•Route differential signal pairs together.

•Minimize the use of vias for high-frequency signals.

The following list contains component placement recommendations.

•Refer to the PCI Local Bus Specification, Revision 2.1 for the placement of the 21143 with relation to the PCI bus.

•Place the 21143 as close to the PHY device as possible.

•Place the PHY device as close to the filters and magnetics as possible.

•Place the filters and magnetics as close to the RJ45 connector as possible.

6.2Suggestions for FCC Compliance

Product designs and their associated applications are unique. Therefore, the designer must consider the total system or module implementation when determining a product design for FCC compliance.

The following information is provided as suggestions only to aid the designer in meeting FCC regulations.

6.2.1Suggestions for Quiet Ground and Power Planes

For quiet ground and power planes, consider the following suggestions:

•Isolate power plane for PLL stability and noise isolation of audio digital-analog converters and amplifiers.

•Partition ground planes to isolate the I/O from common system noise. Do not route any etch across an isolated or partitioned ground plane.

Note: Ground plane splits can affect a signal’s return path back to its source. If the signal return path is along the ground plane underneath the signal etch, any interruption in the ground plane increases the return path loop area, which in turn, increases its ability to radiate.

•Add common-mode chokes to the design at the output of the isolation transformer to isolate the I/O from common system noise.

•Place high-speed signals between power and ground planes to reduce board-level radiation.

The following books are recommended as additional references:

•Fundamentals of Electromagnetic Capability, by William G. Duff

Design Guide 23