Advanced/ZP Technical Product Summary • Page 7
PERIPHERAL COMPONENT INTERCONNECT (PCI) PCISET
The Intel Triton 82430FX PCIset consists of the 82437FX Triton System Controller (TSC), two 82438FX Triton Data Path
(TDP) devices, and one 82371FB PCI ISA/IDE Accelerator (PIIX) bridge chip. The Triton PCIset provides the following
functions:
• CPU interface control
• Integrated L2 write-back cache controller
– Pipelined Burst or standard SRAM
– 256kB or 512kB Direct Mapped
– Integrated Tag Status Bits
•Integrated DRAM controller
– 64-bit path to Memory
– Support for EDO and Fast Page DRAM
– 4 MB to 128 MB main memory
• Fully synchronous PCI bus interface
– 25/30/33 MHz
– PCI to DRAM > 100 Mbytes/sec
– PCI to DRAM posting of 12 Dwords
– 5 Dword buffers for CPU-PCI write posting
– 4 Dword buffers for PCI to Memory bus master
cycles
– Support for up to 5 PCI masters
• Interface between the PCI bus and ISA bus
• Integrated fast IDE interface
– Support for up to 4 devices
– PIO Mode 4 transfers up to 16MB/sec
– Integrated 8 x 32-bit buffer for PCI IDE burst
transfers
• Enhanced Fast DMA controller
• Interrupt controller and steering
• Counters/Timers
•SMI interrupt logic and timer with Fast On/Off mode
82437FX TRITON SYSTEM CONTROLLER (TSC)
The 82437FX provides all control signals necessary to drive a second level cache and the DRAM array, including
multiplexed address signals. It also controls system access to memory and generates snoop controls to maintain cache
coherency. The TSC comes in a 208 pin QFP package.
82438FX TRITON DATA PATH (TDP)
There are two 82438FX components which provide data bus buffering and dual port buffering to the memory array.
Controlled by the 82437FX, the 82438FX devices add one load each to the PCI bus and perform all the necessary byte
and word swapping required. Memory and I/O write buffers are included in these devices. The TDP devices are 100 pin
QFP packages.
82371FB PCI ISA/IDE ACCELERATOR (PIIX)
The 82371FB provides the interface between the PCI and ISA buses and integrates a dual channel fast IDE interface
capable of supporting up to 4 devices, seven 32-bit DMA channels, five 16-bit timer/counters, two eight-channel interrupt
controllers, PCI-to-AT interrupt mapping circuitry, NMI logic, ISA refresh address generation, and PCI/ISA bus
arbitration circuitry. The PIIX comes in a 208-pin QFP package.
TRITON DESIGN CONSIDERATIONSTriton Memory Hole Limitation
Due the design of the Triton chipset, only one memory hole can be active at a time. The user can not set the Base
Memory size to 512 KB and enable the ISA LFB at the same time.
Triton PCI Hold Time Requirement
The Triton chipset provides less hold time than the earlier Neptune and Mercury chipsets on the PCI address and data
lines, but still is within the PCI specification. (The PCI specification calls out a 0 ns minimum hold time.) Some PCI
expansion cards do not meet this requirement, and in fact require more hold time than the Triton chipset provides.
Disabling PCI write bursting will sometimes enable these cards to function.