Intel 82543GC manual

82543GC Gigabit Ethernet Controller

Specification Update

June 18, 2004Revision 2.1

The 82543GC Gigabit Ethernet Controller may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.

Contents

June 18 Revision Page CONTENTS Page REVISION HISTORY 82543GC Gigabit Ethernet Controller Specification Update Note: PREFACE NOMENCLATURE COMPONENT IDENTIFICATION VIA PROGRAMMING INTERFACE GENERAL INFORMATION Summary Table of Changes Page SPECIFICATION CHANGES 1. GMII Setup and Hold Times ERRATA 1. MDI Control Register Returns Incorrect Values 2. Descriptor Queue Maximum Size Limitation 4. Some Registers Cannot Be Accessed During Reset 5. DAC Accesses May Be Interpreted Incorrectly 6. Flash Memory Interface Functions Incorrectly in 64-BitAddress Space 7. Excessive Errors in 100Mb Half-DuplexMode 8. 48 Bit Preambles Sent in 10Mb and 100Mb Operation 9. CRS Detection Takes Too Long in MII Half-DuplexMode 10. DMA Early Receive Function Does Not Work 11. ILOS Bit Copied Incorrectly from EEPROM to Speed Bits 12. Gigabit Half-DuplexMode Operates Incorrectly 13. Zero-BytePCI Bus Writes 14. TCP Segmentation Feature Operates Incorrectly 15. Incorrect Checksum Calculation and Indication 16. Transmitter Affected by Discarding Packets 17. Flash Memory Address Conflicts 18. Packet Buffer Memory Address Conflicts 19. Transmit Packet Corruption of Small Packets 20. Receive Packet Buffer Corruption When Nearly Full 21. Receive Packet Loss in 100Mb Half-DuplexOperation 22. TNCRS Statistic Register Has Live Count in Full-DuplexMode 23. Receive IP Checksum Offload Disabled 24. EEPROM Initializes Software Defined Pins Incorrectly 25. Continuous XOFFs Transmitted When Receive Buffer Is Full 26. Default Speed Selection May Depend on EEPROM Presence 27. Link Status Change Interrupt Only Occurs If Link is Up 28. Early Transmit Feature Does Not Operate Correctly 29. TDO Output Not Floated When JTAG TAP Controller Inactive 30. Initialization Ignores Incorrect EEPROM Signature 31. Internal Loopback Difficulties 32. Collision Pin Not Ignored in TBI Mode 33. Receive Descriptor Writeback Problems for Packets Spanning Multiple Buffers 34. Illegal Oversize Packets Overflow Receive FIFO 35. Transmit Descriptor Writeback Problems with Non-ZeroWTHRESH 36. Bus Initialization with Some Chipsets 37. Use of Receive Delay Timer Ring Register (RDTR) Causes Occasional Lockups 38. Transmit TCP Checksum Incorrectly Modified if Calculated as SPECIFICATION CLARIFICATIONS 1. 0-70CAmbient Temperature Range 2. Receiver Enabling and Disabling DOCUMENTATION CHANGES 1. TX/RX Descriptor Register Addresses 2. Auto Speed Detect Function Requires CTRL.SLU Bit to Be Set 3. Values Programmed to Some Registers While in Reset Do Not Persist 4. JTAG Port Operation 5. Register Summary Uses Improper Page Reference Format 6. Change O_EN_CDET Output to NO_CONNECT 7. Change Recommended Transmit IPG Programming Value for 10/100/1000BASE-T 8. Remove Transmit Report Status Sent Function 9. Remove Transmit DMA Pre-fetchingand Preemption Functions 10. Remove Gigabit Half-DuplexTransmit Burst Timer Control Function (TBT) 11. Remove Adaptive IFS Throttle Function (AIT)