Intel 82543GC manual CONTENTS

82543GC Gigabit Ethernet Controller Specification Update

CONTENTS
CONTENTS .........................................................................................................................................................		3
REVISION HISTORY...........................................................................................................................................		5
PREFACE............................................................................................................................................................		7
NOMENCLATURE ..............................................................................................................................................		7
COMPONENT IDENTIFICATION VIA PROGRAMMING INTERFACE ..............................................................		7
GENERAL INFORMATION .................................................................................................................................		8
82543GC Component Marking Information ..................................................................................................		8
Summary Table of Changes..............................................................................................................................		9
Codes Used in Summary TableS .................................................................................................................		9
SPECIFICATION CHANGES ............................................................................................................................		11
1.	GMII Setup and Hold Times ..............................................................................................................	11
ERRATA	............................................................................................................................................................	11
1.	MDI Control Register Returns Incorrect Values ................................................................................	11
2.	Descriptor Queue Maximum Size Limitation .....................................................................................	11
3.	Late Collision Statistics May Be Incorrect .........................................................................................	11
4.	Some Registers Cannot Be Accessed During Reset ........................................................................	12
5.	DAC Accesses May Be Interpreted Incorrectly .................................................................................	12
6.	Flash Memory Interface Functions Incorrectly in 64-Bit Address Space ...........................................	12
7.	Excessive Errors in 100Mb Half-Duplex Mode ..................................................................................	12
8.	48 Bit Preambles Sent in 10Mb and 100Mb Operation .....................................................................	13
9.	CRS Detection Takes Too Long in MII Half-Duplex Mode ................................................................	13
10.	DMA Early Receive Function Does Not Work ...................................................................................	13
11.	ILOS Bit Copied Incorrectly from EEPROM to Speed Bits ................................................................	13
12.	Gigabit Half-Duplex Mode Operates Incorrectly ................................................................................	13
13.	Zero-Byte PCI Bus Writes .................................................................................................................	14
14.	TCP Segmentation Feature Operates Incorrectly .............................................................................	14
15.	Incorrect Checksum Calculation and Indication ...............................................................................	14
16.	Transmitter Affected by Discarding Packets......................................................................................	14
17.	Flash Memory Address Conflicts.......................................................................................................	15
18.	Packet Buffer Memory Address Conflicts ..........................................................................................	15
19.	Transmit Packet Corruption of Small Packets ...................................................................................	15
20.	Receive Packet Buffer Corruption When Nearly Full.........................................................................	15
21.	Receive Packet Loss in 100Mb Half-Duplex Operation.....................................................................	16
22.	TNCRS Statistic Register Has Live Count in Full-Duplex Mode........................................................	16
23.	Receive IP Checksum Offload Disabled............................................................................................	16
24.	EEPROM Initializes Software Defined Pins Incorrectly .....................................................................	16
25.	Continuous XOFFs Transmitted When Receive Buffer Is Full ..........................................................	17
26.	Default Speed Selection May Depend on EEPROM Presence.........................................................	17

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