Manuals / Brands / Computer Equipment / Network Card / Intel / Computer Equipment / Network Card

Intel 82543GC PREFACE, NOMENCLATURE, COMPONENT IDENTIFICATION VIA PROGRAMMING INTERFACE

1 24

Download 24 pages, 118.44 Kb

82543GC Gigabit Ethernet Controller Specification Update

PREFACE

This document is an update to published specifications. There are two current specification documents:

•82543GC Gigabit Ethernet Controller Datasheet, Intel Corporation.

•OR-2710 82543GC Gigabit Ethernet Controller Developer’s Manual, Intel Corporation.

This document is intended for hardware system manufactures and software developers of applications, operating systems or tools. It contains Specification Changes, Errata, Specification Clarifications, and Documentation Changes.

The changes/errata/clarifications described in this document will be incorporated into the next release of 82543GC Gigabit Ethernet Controller Data Sheet, the 82543GC Gigabit Ethernet Controller Developer’s Manual.

NOMENCLATURE

Specification Changes are modifications to the current published specifications. These changes will be incorporated in the next release of the specifications.

Errata are design defects or errors. Errata may cause 82543GC device behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in the next release of the specifications.

Documentation Changes include typos, errors, or omissions from the current published specifications. These changes will be incorporated in the next release of the specifications.

COMPONENT IDENTIFICATION VIA PROGRAMMING INTERFACE

82543GC steppings can be identified by the following register contents:

82543GC Stepping	Vendor ID	Device ID	Revision Number
A0	8086h	1001h	00h

A1	8086h	1001h	01h
A2	8086h	1001h	02h

The device also provides an identification number through the Test Access Port.

7

Contents

June 18 Revision Page CONTENTS Page REVISION HISTORY 82543GC Gigabit Ethernet Controller Specification Update Note: PREFACE NOMENCLATURE COMPONENT IDENTIFICATION VIA PROGRAMMING INTERFACE GENERAL INFORMATION Summary Table of Changes Page SPECIFICATION CHANGES 1. GMII Setup and Hold Times ERRATA 1. MDI Control Register Returns Incorrect Values 2. Descriptor Queue Maximum Size Limitation 4. Some Registers Cannot Be Accessed During Reset 5. DAC Accesses May Be Interpreted Incorrectly 6. Flash Memory Interface Functions Incorrectly in 64-BitAddress Space 7. Excessive Errors in 100Mb Half-DuplexMode 8. 48 Bit Preambles Sent in 10Mb and 100Mb Operation 9. CRS Detection Takes Too Long in MII Half-DuplexMode 10. DMA Early Receive Function Does Not Work 11. ILOS Bit Copied Incorrectly from EEPROM to Speed Bits 12. Gigabit Half-DuplexMode Operates Incorrectly 13. Zero-BytePCI Bus Writes 14. TCP Segmentation Feature Operates Incorrectly 15. Incorrect Checksum Calculation and Indication 16. Transmitter Affected by Discarding Packets 17. Flash Memory Address Conflicts 18. Packet Buffer Memory Address Conflicts 19. Transmit Packet Corruption of Small Packets 20. Receive Packet Buffer Corruption When Nearly Full 21. Receive Packet Loss in 100Mb Half-DuplexOperation 22. TNCRS Statistic Register Has Live Count in Full-DuplexMode 23. Receive IP Checksum Offload Disabled 24. EEPROM Initializes Software Defined Pins Incorrectly 25. Continuous XOFFs Transmitted When Receive Buffer Is Full 26. Default Speed Selection May Depend on EEPROM Presence 27. Link Status Change Interrupt Only Occurs If Link is Up 28. Early Transmit Feature Does Not Operate Correctly 29. TDO Output Not Floated When JTAG TAP Controller Inactive 30. Initialization Ignores Incorrect EEPROM Signature 31. Internal Loopback Difficulties 32. Collision Pin Not Ignored in TBI Mode 33. Receive Descriptor Writeback Problems for Packets Spanning Multiple Buffers 34. Illegal Oversize Packets Overflow Receive FIFO 35. Transmit Descriptor Writeback Problems with Non-ZeroWTHRESH 36. Bus Initialization with Some Chipsets 37. Use of Receive Delay Timer Ring Register (RDTR) Causes Occasional Lockups 38. Transmit TCP Checksum Incorrectly Modified if Calculated as SPECIFICATION CLARIFICATIONS 1. 0-70CAmbient Temperature Range 2. Receiver Enabling and Disabling DOCUMENTATION CHANGES 1. TX/RX Descriptor Register Addresses 2. Auto Speed Detect Function Requires CTRL.SLU Bit to Be Set 3. Values Programmed to Some Registers While in Reset Do Not Persist 4. JTAG Port Operation 5. Register Summary Uses Improper Page Reference Format 6. Change O_EN_CDET Output to NO_CONNECT 7. Change Recommended Transmit IPG Programming Value for 10/100/1000BASE-T 8. Remove Transmit Report Status Sent Function 9. Remove Transmit DMA Pre-fetchingand Preemption Functions 10. Remove Gigabit Half-DuplexTransmit Burst Timer Control Function (TBT) 11. Remove Adaptive IFS Throttle Function (AIT)