82543GC Gigabit Ethernet Controller Specification Update
Problem: Asserting the collision input signal (COL) can cause the transmitter to hang intermittently in TBI mode.
Implication: When the 82543GC Gigabit Ethernet Controller is in TBI mode, the collision signal is meaningless because receive and transmit channels each have their own dedicated optical fibers. Nevertheless, the pin must be tied off carefully.
Workaround: For TBI mode operation, use a pulldown resistor on the COL input hold it in the deasserted state.
Status: Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.
33. Receive Descriptor Writeback Problems for Packets Spanning Multiple Buffers
Problem: Receive descriptors are typically written back to memory either upon receive interrupts or opportunistically in between writing data buffers. When a received Ethernet packet exceeds the size of a single receive buffer, corrupted receive descriptor writebacks may occur and the controller may hang. The conditions for this erratum are specific:
•The controller is programmed to write back receive descriptors upon a receive interrupt, the interrupt has not yet been triggered, and
•The controller has a programmed descriptor writeback threshold (RXDCTL.WTHRESH), the number of receive descriptors consumed thus far by the packet is equal to or greater than the threshold.
Implication: Corrupted descriptor writebacks may include writing back unconsumed descriptors, descriptor writebacks to incorrect addresses, or writebacks missed altogether. In addition, the device may cease to access the PCI bus or cease packet reception. If the device hangs, a full software or hardware reset is needed.
Workaround: If the system uses buffers smaller than the maximum allowed packet size, take the following precautions:
•Configure the receive interrupt to occur immediately on
•Configure the descriptor writeback threshold WTHRESH to a value that will not result in a writeback in the middle of a packet. Packets may be 1514 bytes or up to 16K bytes if long packets are enabled. It is recommended that the RXDCTL.GRAN bit be set to 1 descriptor and WTHRESH set to the maximum number of descriptor buffers the maximum size packet will consume.
Status: Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.
34. Illegal Oversize Packets Overflow Receive FIFO
Problem: The controller should drop invalid Ethernet packets, but frames exceeding the maximum legal size can overflow the receive FIFO, causing a lock up. This problem has only been reported in a test environment with an IXIA packet generator.
Implication: The 82543GC controller can receive frames up to the size of the receive packet buffer without difficulty. If the 82543GC controller locks up due to an oversize packet, a full software or hardware reset is needed.
Workaround: Driver software should ensure that a minimum of 16K is allocated to the receive FIFO. Packets larger than this size should not be present on the LAN.
Status: Intel does not plan to resolve this erratum in a future stepping of the 82543GC Gigabit Ethernet Controller.
35. Transmit Descriptor Writeback Problems with Non-Zero WTHRESH
Problem: Transmit descriptors are typically written back to memory either upon transmit interrupts or opportunistically in between reading data buffers. When the controller has a programmed writeback threshold (TXDCTL.WTHRESH), it will attempt to write back full descriptors instead of just a status byte. The controller may incorrectly calculate the length of the writeback operation, causing corrupted descriptor writebacks. This erratum is closely related to Erratum #33. “Receive Buffer Writeback Problems for Packets Spanning Multiple Buffers.”
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