82543GC Gigabit Ethernet Controller Specification Update
Summary Table of Changes
The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed 82543GC steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted. This table uses the following notations:
CODES USED IN SUMMARY TABLES
X: | Erratum, Specification Change or Clarification that applies to this stepping. |
Doc: | Document change or update that will be implemented. |
Fix: | This erratum is intended to be fixed in a future stepping of the component. |
Fixed: | This erratum has been previously fixed. |
NoFix: | There are no plans to fix this erratum. |
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification change does not apply to listed stepping.
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| This item is either new or modified from the previous version of the document. |
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| No. | A0 | A1 | A2 | Plans | SPECIFICATION CHANGES | Page | Affected |
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| 1 | X | X | X | NoFix | GMII Setup and Hold Times | 9 | Datasheet |
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| No. | A0 | A1 | A2 | Plans | ERRATA | Page | Notes |
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| 1 | X | X | X | NoFix | MDI Control Register Returns Incorrect Values | 9 |
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| 2 | X | X | X | NoFix | Descriptor Queue Maximum Size Limitation | 9 |
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| 3 | X |
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| Fixed | Late Collision Statistics May Be Incorrect | 9 |
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| 4 | X |
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| Fixed | Some Registers Cannot be Accessed During Reset | 10 |
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| 5 | X | X | X | NoFix | DAC Accesses May Not Be Interpreted Correctly | 10 |
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| 6 | X | X | X | NoFix | Flash Memory Functions Incorrectly in | 10 |
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| 7 | X |
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| Fixed | Excessive Errors in 100Mb | 10 |
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| 8 | X |
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| Fixed | 48 Bit Preambles Sent in 10Mb and 100Mb Operation | 11 |
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| 9 | X |
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| Fixed | CRS Detection Takes Too Long in MII | 11 |
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| 10 | X | X | X | NoFix | DMA Early Receive Function Does Not Work | 11 |
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| 11 | X |
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| Fixed | ILOS Bit Copied Incorrectly from EEPROM to Speed Bits | 11 |
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| 12 | X | X | X | NoFix | Gigabit | 11 |
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| 13 | X | X | X | NoFix | 12 |
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| 14 | X | X | X | NoFix | TCP Segmentation Feature Operates Incorrectly | 12 |
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| 15 | X | X |
| Fixed | Incorrect Checksum Calculation and Indication | 12 |
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| 16 | X |
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| Fixed | Transmitter Affected by Discarding Packets | 12 |
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| 17 | X |
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| Fixed | Flash Memory Address Conflicts | 13 |
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| 18 | X | X | X | NoFix | Packet Buffer Memory Address Conflicts | 13 |
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| 19 | X |
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| Fixed | Transmit Packet Corruption of Small Packets | 13 |
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| 20 | X |
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| Fixed | Receive Packet Buffer Corruption When Nearly Full | 13 |
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| 21 | X | X |
| Fixed | Receive Packet Loss in 100Mb | 14 |
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| 22 | X | X | X | NoFix | TNCRS Statistic Register Has Live Count in | 14 |
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| 23 |
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| X | NoFix | Receive IP Checksum Offload Disabled | 14 |
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| 24 | X | X | X | NoFix | EEPROM Initializes Software Defined Pins Incorrectly | 14 |
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| 25 | X | X | X | NoFix | Continuous XOFFs Transmitted When Receive Buffer Is Full | 15 |
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