Intel 80C51FA ICC vs Frequency, ICC Test Condition, Active Mode All other pins disconnected

Models: 80C51FA 83C51FA

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AUTOMOTIVE 80C51FA/83C51FA

270501 ±7

ICC Max at other frequencies is given by: Active Mode

ICC Max e (3 c Osc Freq) a 4 Idle Mode

ICC Max e (0.49 c Osc Freq) a 1.6 Where Osc Freq is in MHz, ICC is in mA.

270501 ±9

TCLCH e TCHCL e 5 ns

Figure 8. ICC Test Condition Idle Mode. All other pins disconnected.

270501 ±8

TCLCH e TCHCL e 5 ns

270501 ±10

Power Down Mode.

VCC e 2.0V to 5.5V.

270501 ±11

Figure 10. Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH e TCHCL e 5 ns.

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Contents

MEMORY ORGANIZATION 80C51FA/83C51FA EVENT-CONTROL CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERAutomotive AUTOMOTIVE 80C51FA/83C51FA Figure 1. 83C51FA Block Diagram80C51FA/83C51FA PRODUCT OPTIONS Table 1. Temperature OptionsFigure 2. MCS 51 Microcontroller Product Family Nomenclature Diagrams are for pin reference only. Package sizes are not to scale PIN DESCRIPTIONSPort Pin Alternate FunctionPort Pin OSCILLATOR CHARACTERISTICSAlternate Function Figure 4. Oscillator ConnectionsIDLE MODE POWER DOWN MODEDESIGN CONSIDERATION ONCE MODESymbol ABSOLUTE MAXIMUM RATINGSParameter signal may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an Address Latch SymbolParameter UnitFigure 9. ICC Test Condition Power Down Mode Figure 7. ICC Test Condition, Active Mode All other pins disconnectedAll other pins disconnected VCC e 2.0V to Figure 6. ICC vs FrequencyEXTERNAL MEMORY CHARACTERISTICS EXPLANATION OF THE AC SYMBOLSEXTERNAL DATA MEMORY READ CYCLE EXTERNAL PROGRAM MEMORY READ CYCLEEXTERNAL DATA MEMORY WRITE CYCLE AUTOMOTIVE 80C51FA/83C51FASHIFT REGISTER MODE TIMING WAVEFORMS SERIAL PORT TIMING-SHIFT REGISTER MODEEXTERNAL CLOCK DRIVE EXTERNAL CLOCK DRIVE WAVEFORMDATASHEET REVISION HISTORY AC TESTING INPUT, OUTPUT WAVEFORMSFLOAT WAVEFORMS