Intel BX80637G2010 - page 102

Processor Land and Signal Information

102 Datasheet, Volume 1

VCCAXG AB36 PWR

VCCAXG AB37 PWR

VCCAXG AB38 PWR

VCCAXG AB39 PWR

VCCAXG AB40 PWR

VCCAXG AC33 PWR

VCCAXG AC34 PWR

VCCAXG AC35 PWR

VCCAXG AC36 PWR

VCCAXG AC37 PWR

VCCAXG AC38 PWR

VCCAXG AC39 PWR

VCCAXG AC40 PWR

VCCAXG T33 PWR

VCCAXG T34 PWR

VCCAXG T35 PWR

VCCAXG T36 PWR

VCCAXG T37 PWR

VCCAXG T38 PWR

VCCAXG T39 PWR

VCCAXG T40 PWR

VCCAXG U33 PWR

VCCAXG U34 PWR

VCCAXG U35 PWR

VCCAXG U36 PWR

VCCAXG U37 PWR

VCCAXG U38 PWR

VCCAXG U39 PWR

VCCAXG U40 PWR

VCCAXG W33 PWR

VCCAXG W34 PWR

VCCAXG W35 PWR

VCCAXG W36 PWR

VCCAXG W37 PWR

VCCAXG W38 PWR

VCCAXG Y33 PWR

VCCAXG Y34 PWR

VCCAXG Y35 PWR

VCCAXG Y36 PWR

VCCAXG Y37 PWR

VCCAXG Y38 PWR

VCCAXG_SENSE L32 Analog O

VCCIO A11 PWR

VCCIO A7 PWR

VCCIO AA3 PWR

VCCIO AB8 PWR

VCCIO AF8 PWR

Table 8-1. Processor Land List by

Land Name

Land Name Land # Buffer Type Dir.

VCCIO AG33 PWR

VCCIO AJ16 PWR

VCCIO AJ17 PWR

VCCIO AJ26 PWR

VCCIO AJ28 PWR

VCCIO AJ32 PWR

VCCIO AK15 PWR

VCCIO AK17 PWR

VCCIO AK19 PWR

VCCIO AK21 PWR

VCCIO AK23 PWR

VCCIO AK27 PWR

VCCIO AK29 PWR

VCCIO AK30 PWR

VCCIO B9 PWR

VCCIO D10 PWR

VCCIO D6 PWR

VCCIO E3 PWR

VCCIO E4 PWR

VCCIO G3 PWR

VCCIO G4 PWR

VCCIO J3 PWR

VCCIO J4 PWR

VCCIO J7 PWR

VCCIO J8 PWR

VCCIO L3 PWR

VCCIO L4 PWR

VCCIO L7 PWR

VCCIO M13 PWR

VCCIO N3 PWR

VCCIO N4 PWR

VCCIO N7 PWR

VCCIO R3 PWR

VCCIO R4 PWR

VCCIO R7 PWR

VCCIO U3 PWR

VCCIO U4 PWR

VCCIO U7 PWR

VCCIO V8 PWR

VCCIO W3 PWR

VCCIO_SEL P33 N/A O

VCCIO_SENSE AB4 Analog O

VCCPLL AK11 PWR

VCCPLL AK12 PWR

VCCSA H10 PWR

VCCSA H11 PWR

VCCSA H12 PWR

Table 8-1. Processor Land List by

Land Name

Land Name Land # Buffer Type Dir.

Contents

Main 2 Contents Page Page Figures Tables Page Revision History 1 Figure 1-1. Desktop Processor Platform DDR3 PECI Intel Processor 1.1 Processor Feature Details 1.1.1 Supported Technologies 1.2 Interfaces 1.2.1 System Memory Support 1.2.2 PCI Express* Page 1.2.3 Direct Media Interface (DMI) 1.2.4 Platform Environment Control Interface (PECI) 1.2.5 Processor Graphics 1.2.6 Intel Flexible Display Interface (Intel FDI) 1.3 Power Management Support 1.3.1 Processor Core 1.3.2 System 1.3.3 Memory Controller 1.3.4 PCI Express* 1.4 Processor SKU Definitions 1.5 Package Introduction 18 Datasheet, Volume 1 1.6 Processor Compatibility PCH Figure 1-2. Desktop Processor Compatibility Diagram VCCIO VR VDDQ VR VCore VR VCCSA VR 1.7 Terminology Table 1-2. Terminology (Sheet 1 of 3) Table 1-2. Terminology (Sheet 2 of 3) Table 1-2. Terminology (Sheet 3 of 3) 1.8 Related Documents Table 1-3. Related Documents 2 2.1 System Memory Interface 2.1.1 System Memory Technology Supported 2.1.2 System Memory Timing Support Table 2-2. Supported UDIMM Module Configurations Table 2-3. Supported SO-DIMM Module Configurations (AIO Only) 2.1.3 System Memory Organization Modes 2.1.3.1 Single-Channel Mode 2.1.3.2 Dual-Channel Mode Intel Flex Memory Technology Mode 2.1.4 Rules for Populating Memory Slots 2.1.5 Technology Enhancements of Intel Fast Memory Access (Intel FMA) 2.1.5.1 Just-in-Time Command Scheduling 2.1.5.2 Command Overlap 2.1.5.3 Out-of-Order Scheduling 2.1.6 Data Scrambling 2.2 PCI Express* Interface 2.2.1 PCI Express* Architecture 2.2.1.1 Transaction Layer 2.2.1.2 Data Link Layer 2.2.1.3 Physical Layer 2.2.2 PCI Express* Configuration Mechanism 2.2.3 PCI Express* Port 2.2.3.1 PCI Express* Lanes Connection 2.3 Direct Media Interface (DMI) 2.3.1 DMI Error Flow 2.3.2 Processor / PCH Compatibility Assumptions 2.3.3 DMI Link Down 2.4 Processor Graphics Controller (GT) 2.4.1 3D and Video Engines for Graphics Processing 2.4.1.1 3D Engine Execution Units 2.4.1.2 3D Pipeline 2.4.1.3 Video Engine 2.4.1.4 2D Engine 2.4.2 Processor Graphics Display 2.4.2.1 Display Planes 2.4.2.2 Display Pipes 2.4.2.3 Display Ports 2.4.3 Intel Flexible Display Interface (Intel FDI) 2.4.4 Multi Graphics Controllers Multi-Monitor Support 2.5 Platform Environment Control Interface (PECI) 2.6 Interface Clocking 2.6.1 Internal Clocking Requirements 3 3.1 Intel Virtualization Technology (Intel VT) 3.1.3 Intel Virtualization Technology (Intel VT) for Directed I/O (Intel VT-d) Objectives 3.1.4 Intel Virtualization Technology (Intel VT) for Directed I/O (Intel VT-d) Features 3.2 Intel Trusted Execution Technology (Intel TXT) 3.3 Intel Hyper-Threading Technology (Intel HT Technology) 3.4 Intel Turbo Boost Technology 3.4.1 Intel Turbo Boost Technology Frequency 3.4.2 Intel Turbo Boost Technology Graphics Frequency 3.5 Intel Advanced Vector Extensions (Intel AVX) 3.6 Security and Cryptography Technologies 3.6.1 Intel Advanced Encryption Standard New Instructions (Intel AES-NI) 3.6.2 PCLMULQDQ Instruction 3.6.3 RDRAND Instruction 3.7 Intel 64 Architecture x2APIC 3.8 Supervisor Mode Execution Protection (SMEP) 3.9 Power Aware Interrupt Routing (PAIR) 4 G0 Working G3 Mechanical Off G1 Sleeping 4.1 Advanced Configuration and Power Interface (ACPI) States Supported The ACPI states supported by the processor are described in this section. 4.1.3 Integrated Memory Controller States 4.1.1 System States 4.1.2 Processor Core / Package Idle States 4.1.4 PCI Express* Link States 4.1.5 Direct Media Interface (DMI) States 4.1.7 Interface State Combinations 4.1.6 Processor Graphics Controller States Table 4-4. PCI Express* Link States 4.2 Processor Core Power Management 4.2.1 Enhanced Intel SpeedStep Technology 4.2.2 Low-Power Idle States Processor Package State Core 0 State C1 C1E C6C3 Core 1 State C0 4.2.3 Requesting Low-Power Idle States 4.2.4 Core C-states 4.2.4.1 Core C0 State 4.2.4.2 Core C1 / C1E State 4.2.4.3 Core C3 State 4.2.4.4 Core C6 State 4.2.4.5 C-State Auto-Demotion 4.2.5 Package C-States 4.2.5.1 Package C0 4.2.5.2 Package C1/C1E 4.2.5.3 Package C3 State 4.2.5.4 Package C6 State 4.3 Integrated Memory Controller (IMC) Power Management 4.3.1 Disabling Unused System Memory Outputs 4.3.2 DRAM Power Management and Initialization 4.3.2.1 Initialization Role of CKE 4.3.2.2 Conditional Self-Refresh 4.3.2.3 Dynamic Power Down Operation 4.3.2.4 DRAM I/O Power Management 4.3.3 DDR Electrical Power Gating (EPG) 4.4 PCI Express* Power Management 4.5 DMI Power Management 4.6 Graphics Power Management 4.6.1 Intel Rapid Memory Power Management (Intel RMPM) (also known as CxSR) 4.6.2 Intel Graphics Performance Modulation Technology (Intel GPMT) 4.7 Graphics Thermal Power Management Page 5 Page 6 6.1 System Memory Interface Signals Table 6-2. Memory Channel A Signals 6.2 Memory Reference and Compensation Signals Table 6-3. Memory Channel B Signals Table 6-4. Memory Reference and Compensation 6.3 Reset and Miscellaneous Signals Table 6-5. Reset and Miscellaneous Signals 6.4 PCI Express*-based Interface Signals 6.5 Intel Flexible Display (Intel FDI) Interface Signals Table 6-6. PCI Express* Graphics Interface Signals Table 6-7. Intel Flexible Display (Intel FDI) Interface 6.6 Direct Media Interface (DMI) Signals 6.7 Phase Lock Loop (PLL) Signals 6.8 Test Access Points (TAP) Signals Table 6-8. Direct Media Interface (DMI) Sign als Processor to PCH Serial Interface Table 6-9. Phase Lock Loop (PLL) Signals Table 6-10. Test Access Points (TAP) Signals 6.9 Error and Thermal Protection Signals Table 6-11. Error and Thermal Protection Signals 6.10 Power Sequencing Signals Table 6-12. Power Sequencing Signals 6.11 Processor Power Signals 6.12 Sense Signals Table 6-13. Processor Power Signals Table 6-14. Sense Signals 6.13 Ground and Non-Critical to Function (NCTF) Signals 6.14 Processor Internal Pull-Up / Pull-Down Resistors Table 6-15. Ground and Non-Critical to Function (NCTF) Signals Table 6-16. Processor Internal Pull-Up / Pull-Down Resistors 7 7.1 Power and Ground Lands 7.2 Decoupling Guidelines 7.2.1 Voltage Rail Decoupling 7.3 Processor Clocking (BCLK[0], BCLK#[0]) 7.3.1 Phase Lock Loop (PLL) Power Supply 7.4 VCC Voltage Identification (VID) Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 1 of 3) Table 7-1. VR 12.0 Volt age Identification Definition (Sheet 2 of 3) Table 7-1. VR 12.0 Voltage Identification Definition (Sheet 3 of 3) 7.5 System Agent (SA) VCC VID 7.6 Reserved or Unused Signals 7.7 Signal Groups Table 7-2. Signal Groups (Sheet 1 of 2) 7.8 Test Access Port (TAP) Connection 7.9 Storage Conditions Specifications 7.10 DC Specifications 7.10.1 Voltage and Current Specifications Page Table 7-5. Processor System Agent I/O Buffer Supply DC Voltage and Current Specifications Table 7-6. Processor Graphics VID based (VAXG) Supply DC Voltage and Current Specifications Table 7-7. DDR3 Signal Group DC Specifications (Sheet 1 of 2) Table 7-7. D DR3 Signal Group DC Specifications (Sheet 2 of 2) Table 7-8. Control Sideband and TAP Signal Group DC Specifications Table 7-9. PCI Express* DC Specifications 7.11 Platform Environmental Control Interface (PECI) DC Specifications 7.11.1 PECI Bus Architecture 7.11.2 DC Characteristics PECI Ground PECI Low Range Maximum V Minimum V Page 8 Information 8.1 Processor Land Assignments Processor Land and Signal Information 94 Datasheet, Volume 1 Figure 8-1. LGA Socket Land Map Page Page Page Page Page Page Page Page Page Page Page Processor Land and Signal Information Page Page 9 DDR Data Swizzling Table 9-1. DDR Data Swizz ling Table Channel A Table 9-1. DDR Data Swizzling Table Channel A Table 9-2. D DR Data Swizzling table Channel B Table 9-2. DDR Data Swizzling table Channel B