Intel BX80637G2010 4.2 Processor Core Power Management

Power Management

50 Datasheet, Volume 1

4.2 Processor Core Power Management

While executing code, Enhanced Intel SpeedStep Technology optimizes the processor’s

frequency and core voltage based on workload. Each frequency and voltage operating

point is defined by ACPI as a P-state. When the processor is not executing code, it is

idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power

C-states have longer entry and exit latencies.

The following are the key features of Enhanced Intel SpeedStep Technology:

• Multiple frequency and voltage points for optimal performance and power

efficiency. These operating points are known as P-states.

• Frequency selection is software controlled by writing to processor MSRs. The

voltage is optimized based on the selected frequency and the number of active

processor cores.

— If the target frequency is higher than the current frequency, VCC is ramped up

in steps to an optimized voltage. This voltage is signaled by the SVID bus to the

voltage regulator. Once the voltage is established, the PLL locks on to the

target frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the

target frequency, then transitions to a lower voltage by signaling the target

voltage on SVID bus.

— All active processor cores share the same frequency and voltage. In a multi-

core processor, the highest frequency P-state requested amongst all active

cores is selected.

— Software-requested transitions are accepted at any time. If a previous

transition is in progress, the new transition is deferred until the previous

transition is completed.

• The processor controls voltage ramp rates internally to ensure glitch-free

transitions.

• Because there is low transition latency between P-states, a significant number of

transitions per-second are possible.

When the processor is idle, low-power idle states (C-states) are used to save power.

More power savings actions are taken for numerically higher C-states. However, higher

C-states have longer exit and entry latencies. Resolution of C-states occur at the

thread, processor core, and processor package level. Thread-level C-states are

available if Intel® HT Technology is enabled.

Caution: Long term reliability cannot be assured unless all the Low Power Idle States are

enabled.