Intel BX80637G2010 2.4.3 Intel Flexible Display Interface (Intel FDI), 2.4.4 Multi Graphics Controllers Multi-Monitor Support

Datasheet, Volume 1 37

Interfaces

The display pipe blends and synchronizes pixel data received from one or more display

planes and adds the timing of the display output device upon which the image is

displayed.

The display pipes A, B, and C operate independently of each other at the rate of 1 pixel

per clock. They can attach to any of the display ports. Each pipe sends display data to

eDP* or to the PCH over the Intel® Flexible Display Interface (Intel® FDI).

The display ports consist of output logic and pins that transmit the display data to the

associated encoding logic and send the data to the display device (that is, LVDS,

HDMI*, DVI, SDVO, and so on). All display interfaces connecting external displays are

now repartitioned and driven from the PCH. Refer to the PCH datasheet for more details

on display port support.

2.4.3 Intel® Flexible Display Interface (Intel® FDI)

Intel® Flexible Display Interface (Intel® FDI) is a proprietary link for carrying display

traffic from the Processor Graphics controller to the PCH display I/Os. Intel FDI

supports two or three independent channels – one for pipe A, one for pipe B, and one

for Pipe C.

Channels A and B have a maximum of four transmit (Tx) differential pairs used for

transporting pixel and framing data from the display engine in two display

configurations. In three display configurations Channel A has 4 transmit (Tx)

differential pairs while Channel B and C have two transmit (Tx) differential pairs.

• Each channel has four transmit (Tx) differential pairs used for transporting pixel

and framing data from the display engine

• Each channel has one single-ended LineSync and one FrameSync input (1-V CMOS

signaling)

• One display interrupt line input (1-V CMOS signaling)

• Intel FDI may dynamically scale down to 2X or 1X based on actual display

bandwidth requirements

• Common 100-MHz reference clock

• Each channel transports at a rate of 2.7 Gbps

• PCH supports end-to-end lane reversal across both channels (no reversal support

required in the processor)

2.4.4 Multi Graphics Controllers Multi-Monitor Support

The processor supports simultaneous use of the Processor Graphics Controller (GT) and

a x16 PCI Express* Graphics (PEG) device.

The processor supports a maximum of 2 displays connected to the PEG card in parallel

with up to 2 displays connected to the processor and PCH.

Note: When supporting Multi Graphics Multi Monitors, “drag and drop” between monitors and

the 2x8 PEG is not supported.